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1. 发明授权

US5390173A Packet format in hub for packet data communications system 失效
标题翻译：分组数据通信系统中心的数据包格式
公开(公告)号：US5390173A
公开(公告)日：1995-02-14
申请号：US965651
申请日：1992-10-22
申请人： Barry A. Spinney , Robert J. Simcoe , Robert E. Thomas , George Varghese
发明人： Barry A. Spinney , Robert J. Simcoe , Robert E. Thomas , George Varghese
IPC分类号： H04L12/46 , H04J3/26
CPC分类号： H04L12/46
摘要： A packet data communication network employs a local switch, router or bridge device functioning to transfer packets between segments of a larger network. When packets enter this device, an address translation is performed to generate local source and destination addresses which are much shorter than the globally-unique addresses contained in the packet as dictated by the protocol. These local addresses are inserted in a header that is added to the packet, in addition to any header already contained in the packet. This added header travels with the packet through the local switch, router or bridge device, but then is stripped off before the packet is sent out onto another network segment. The added header may also contain other information, such as a local name for the source and destination segment (link), as well as status information that is locally useful, but not part of the packet protocol and not necessary for transmission with the packet throughout the network. Local congestion information, results of address translations, and end-of-message information, are examples of such status information.
摘要翻译：分组数据通信网络采用本地交换机，路由器或网桥设备，其功能是在较大网络的段之间传送分组。当分组进入该设备时，执行地址转换以产生比协议所指示的包中包含的全局唯一地址短的本地源和目的地址。这些本地地址除了已经包含在数据包中的任何头部之外，都插入到添加到数据包的头中。该添加的报头通过本地交换机，路由器或网桥设备与数据包一起运行，但在数据包发送到另一个网段之前被剥离。添加的报头还可以包含其他信息，例如源和目的地段（链接）的本地名称以及本地有用的状态信息，但不是分组协议的一部分，并且不一定与数据包一起传输网络。本地拥塞信息，地址转换结果和消息结束信息是这种状态信息的示例。

2. 发明授权

US5303391A Fast arbiter having easy scaling for large numbers of requesters, large numbers of resource types with multiple instances of each type, and selectable queuing disciplines 失效
标题翻译：快速仲裁器可轻松扩展大量请求者，大量资源类型，每种类型的多个实例以及可选排队规则
公开(公告)号：US5303391A
公开(公告)日：1994-04-12
申请号：US1006
申请日：1993-01-06
申请人： Robert J. Simcoe , Robert E. Thomas
发明人： Robert J. Simcoe , Robert E. Thomas
IPC分类号： G06F13/362 , G06F13/14
CPC分类号： G06F13/362
摘要： A plug-in logic board for use in an arbitration mechanism is disclosed. The disclosed arbitration mechanism includes two or more request processing units, two or more grant processing units and a common broadcast medium. The request processing units and the grant processing units use the common broadcast medium to control the coupling between requesters and resources on a first come, first served basis. The disclosed logic board includes a request processing unit coupled to the common broadcast medium, a grant processing unit coupled to the common broadcast medium, and an input/output unit coupled to an electronic operating device. The input/output unit passes a resource type request signal from the electronic operating device to the request processing unit, and passes a status signal received from the electronic operating device to the grant processing unit. The input/output unit further outputs a grant signal received from the request processing unit to the electronic operating device. The disclosed logic board further includes a means, responsive to said resource type request signal, said status signal, and said grant signal, for coupling a requester type electronic operating device to a resource type electronic operating device using a resource access path.
摘要翻译：公开了一种用于仲裁机制的插件逻辑板。所公开的仲裁机制包括两个或更多个请求处理单元，两个或更多授权处理单元和公共广播介质。请求处理单元和授权处理单元使用公共广播介质以先到先得的方式来控制请求者和资源之间的耦合。所公开的逻辑板包括耦合到公共广播介质的请求处理单元，耦合到公共广播介质的授权处理单元和耦合到电子操作设备的输入/输出单元。输入/输出单元将资源类型请求信号从电子操作装置传递到请求处理单元，并将从电子操作装置接收到的状态信号传递到许可处理单元。输入/输出单元还将从请求处理单元接收的授权信号输出到电子操作装置。所公开的逻辑板还包括响应于所述资源类型请求信号，所述状态信号和所述授权信号的装置，用于使用资源访问路径将请求者类型的电子操作装置耦合到资源型电子操作装置。

3. 发明授权

US5418967A Fast arbiter having easy scaling for large numbers of requesters, large numbers of resource types with multiple instances of each type, and selectable queuing disciplines 失效
标题翻译：快速仲裁器可轻松扩展大量请求者，大量资源类型，每种类型的多个实例以及可选排队规则
公开(公告)号：US5418967A
公开(公告)日：1995-05-23
申请号：US995
申请日：1993-01-06
申请人： Robert J. Simcoe , Robert E. Thomas
发明人： Robert J. Simcoe , Robert E. Thomas
IPC分类号： G06F13/362 , G06F13/00
CPC分类号： G06F13/362
摘要： A computer system having an arbitration mechanism for controlling the coupling order between a plurality of requesters and a plurality of resources, where each resource has an associated resource type. The arbitration mechanism includes a plurality of request processing units, each associated with one of the plurality of requesters. The request processing units receive resource type request signals from an associated requester. The arbitration mechanism also includes a plurality of grant processing units, each associated with one of the plurality of resources. The grant processing units monitor a status signal from its associated resource. The arbitration mechanism further includes a common broadcast medium which is coupled to all of the request processing units and grant processing units. The request and grant processing units arbitrate for access to the common broadcast medium, and then use the common broadcast medium to exchange information to control the coupling order between the plurality of resources and the plurality of requesters in the computer system. When a request processing unit and a grant processing unit have arbitrated for the coupling of a particular requester and a particular resource, a controller establishes a connection between the requester and the resource through a resource access path.
摘要翻译：一种具有用于控制多个请求者与多个资源之间的耦合顺序的仲裁机制的计算机系统，其中每个资源具有相关联的资源类型。仲裁机制包括多个请求处理单元，每个请求处理单元与多个请求者之一相关联。请求处理单元从相关联的请求者接收资源类型请求信号。仲裁机制还包括多个授权处理单元，每个授权处理单元与多个资源之一相关联。授权处理单元监视其相关资源的状态信号。仲裁机制还包括与所有请求处理单元和授权处理单元耦合的公共广播介质。请求和授权处理单元仲裁访问公共广播媒体，然后使用公共广播媒体交换信息，以控制计算机系统中的多个资源与多个请求者之间的耦合顺序。当请求处理单元和授权处理单元对特定请求者和特定资源的耦合进行仲裁时，控制器通过资源访问路径建立请求者与资源之间的连接。

4. 发明授权

US5995995A Apparatus and method for scheduling virtual circuit data for DMA from a host memory to a transmit buffer memory 失效
标题翻译：用于将DMA的虚拟电路数据从主机存储器调度到发送缓冲存储器的装置和方法
公开(公告)号：US5995995A
公开(公告)日：1999-11-30
申请号：US712698
申请日：1996-09-12
申请人： Robert E. Thomas , Robert J. Simcoe , Peter J. Roman , Anna Charny , Wing Cheung
发明人： Robert E. Thomas , Robert J. Simcoe , Peter J. Roman , Anna Charny , Wing Cheung
IPC分类号： H04L12/56 , H04Q11/04 , G06F9/00
CPC分类号： H04L12/5602 , H04Q11/0478 , H04L2012/5651 , H04L2012/5679
摘要： A method of scheduling the transmission of cells from a network node involves storing entries in a schedule table at predetermined locations, wherein each location represents a point in time at which a cell is to be transmitted. Each entry in the table contains a pointer to a list of virtual circuits having cells scheduled for transmission at the time corresponding to the location of the entry in the table. When a VC has a cell to be transmitted at a particular time, the VC is queued to the head, rather than the tail, of the list of VCs pointed to by the pointer located at the entry in the table corresponding to the time at which the cell is to be transmitted. The VC is therefore the first VC transmitted from the list of VCs.
摘要翻译：调度来自网络节点的小区的传输的方法包括在预定位置处存储调度表中的条目，其中每个位置表示要发送小区的时间点。表中的每个条目包含指向在与表中的条目的位置相对应的时间被调度用于传输的小区的虚拟电路的列表的指针。当VC具有要在特定时间发送的小区时，VC排队到位于表中对应于表的时间的指针指向的VC列表的头部而不是尾部，传输单元。因此，VC是从VC列表中发送的第一个VC。

5. 发明授权

US4924463A Data coding method for use in digital communication systems 失效
标题翻译：用于数字通信系统的数据编码方法
公开(公告)号：US4924463A
公开(公告)日：1990-05-08
申请号：US383439
申请日：1989-07-24
申请人： Robert E. Thomas , Jeffrey L. Cooper , Robert J. Simcoe
发明人： Robert E. Thomas , Jeffrey L. Cooper , Robert J. Simcoe
IPC分类号： H04J3/06 , H04L25/49
CPC分类号： H04L25/4908 , H04J3/0605
摘要： A data coding method for digital communication systems is disclosed. In two embodiments, every four bits of data in a first data channel are mapped to a five bit code symbol. The five bit code symbols are chosen to have a duty cycle of 40 to 60 percent. In the first embodiment, a second channel of data is optionally interleaved with the encoded first channel data by placing single bits from the second channel every sixth bit in the data stream between each five bit code symbol. A plurality of synchronizing words are each formed from other pairs of five bit code symbols, and, in the two channel embodiment, the optional two bits of data from the second channel. The synchronizing words also have a duty cycle of 40 to 60 percent, and further have the characteristic that their bit patterns can only occur where they are placed in a stream of encoded data. This enables them to be easily recognized in a data stream for both synchronization of a communication element with the encoded data stream, and conveyance of control information between elements in the system. The second channel can also be utilized for conveyance of control information, as a separate data channel, or in a third embodiment, to provide an exact 50 percent duty cycle for a "balanced" code in which every four bits of data are mapped to a six bit code symbol. The maximum run length of this code is limited to five if the second channel is used, and four if it is not used.
摘要翻译：公开了一种用于数字通信系统的数据编码方法。在两个实施例中，将第一数据信道中的每四位数据映射到五位代码符号。五位代码符号被选择为具有40％至60％的占空比。在第一实施例中，第二数据通道可选地与编码的第一通道数据交错，通过在每个五位代码符号之间的每数据流中的每第六位放置来自第二通道的单个位。多个同步字各自由其他五比特码符号对形成，并且在两个信道实施例中，来自第二信道的可选的两位数据。同步字还具有40至60％的占空比，并且还具有它们的位模式只能在它们被放置在编码数据流中的情况下发生的特征。这使得它们能够容易地识别为用于通信元件与编码数据流的同步的数据流，以及系统中的元件之间的控制信息的传送。第二通道还可以用作输送控制信息，作为单独的数据通道，或者在第三实施例中，为“平衡”代码提供精确的50％占空比，其中每四位数据映射到六位代码符号。如果使用第二个通道，则此代码的最大运行长度被限制为5个，如果不使用则为4个。

6. 发明授权

US5265257A Fast arbiter having easy scaling for large numbers of requesters, large numbers of resource types with multiple instances of each type, and selectable queuing disciplines 失效
标题翻译：快速仲裁器可轻松扩展大量请求者，大量资源类型，每种类型的多个实例以及可选排队规则
公开(公告)号：US5265257A
公开(公告)日：1993-11-23
申请号：US542856
申请日：1990-06-22
申请人： Robert J. Simcoe , Robert E. Thomas
发明人： Robert J. Simcoe , Robert E. Thomas
IPC分类号： G06F13/362 , G06F13/00
CPC分类号： G06F13/362
摘要： A fast arbiter for handling a large number of types of resources with multiple instances of each type of resource is provided. During a first cycle a request logic circuit broadcasts a request for a preselected type of resource onto a broadcast medium. During a second cycle a grant logic circuit broadcasts a queue position onto the broadcast medium for the preselected type of resource. Also, during the second cycle the request logic circuit stores the queue position. After an asynchronous wait for an instance of the requested type of resource to become free, a third cycle begins wherein the first grant logic circuit broadcasts an indication that a free instance of the preselected type of resource is available. During a fourth cycle the requester is granted access to the free instance of the preselected type of resource.

7. 发明授权

US5960215A Transmit data FIFO for flow controlled data 失效
标题翻译：发送流量控制数据的数据FIFO
公开(公告)号：US5960215A
公开(公告)日：1999-09-28
申请号：US712742
申请日：1996-09-12
申请人： Robert E. Thomas , Robert J. Simcoe , Peter J. Roman , Koichi Tanaka
发明人： Robert E. Thomas , Robert J. Simcoe , Peter J. Roman , Koichi Tanaka
IPC分类号： G06F13/12 , H04L12/56 , H04Q11/04 , G06F13/00
CPC分类号： H04L47/10 , G06F13/128 , H04L49/309 , H04L49/90 , H04L49/901 , H04L49/9078 , H04Q11/0478 , H04L2012/5652 , H04L2012/5658 , H04L2012/5679 , H04L2012/5681
摘要： A method and apparatus for transferring data units between a host memory and a peripheral interface, the data units being subject to a flow control mechanism whereby some of said data units are flow controlled and some of said data units are not. Two transmit buffer memories are coupled to the peripheral interface; one for storing controlled data units to be transferred to the peripheral interface and the other for storing uncontrolled data units to be transferred to the peripheral interface. A single request buffer stores successive requests for data to be transferred from a host memory to either of the two transmit buffer memories. Data transfer circuitry transfers data from the host memory to either of the two transmit buffer memories in response to the requests stored in the request buffer. The data transfer circuitry is prevented from transferring further data from the host memory to the transmit buffer memory storing the controlled data units when it is determined that there is not enough room in the transmit buffer memory storing the controlled data units to accommodate another data unit. The data transfer circuitry is allowed, however, to transfer further data from the host memory to the transmit buffer memory storing the uncontrolled data units.
摘要翻译：一种用于在主机存储器和外围接口之间传送数据单元的方法和装置，所述数据单元经受流量控制机制，由此一些所述数据单元被流控制，并且所述数据单元中的一些不是。两个发送缓冲存储器耦合到外围接口; 一个用于存储要传送到外围接口的受控数据单元，另一个用于存储要传送到外围接口的不受控制的数据单元。单个请求缓冲器将要从主机存储器传送的数据的连续请求存储到两个发送缓冲存储器中的任一个。数据传输电路响应于存储在请求缓冲器中的请求，将数据从主机存储器传送到两个发送缓冲存储器中的任一个。当确定存储受控数据单元以容纳另一个数据单元的发送缓冲存储器中没有足够的空间时，防止数据传送电路将另外的数据从主机存储器传送到存储受控数据单元的发送缓冲存储器。然而，允许数据传输电路将另外的数据从主机存储器传送到存储非受控数据单元的发送缓冲存储器。

8. 发明授权

US5313641A Fast arbiter having easy scaling for large numbers of requesters, large numbers of resource types with multiple instances of each type, and selectable queing disciplines 失效
标题翻译：快速仲裁器可以方便地为大量的请求者定标，大量的资源类型，每种类型的多个实例，以及可选择的排队规则
公开(公告)号：US5313641A
公开(公告)日：1994-05-17
申请号：US1134
申请日：1993-01-06
申请人： Robert J. Simcoe , Robert E. Thomas
发明人： Robert J. Simcoe , Robert E. Thomas
IPC分类号： G06F13/362 , G06F13/14
CPC分类号： G06F13/362
摘要： An arbitration mechanism for controlling a coupling order between a number of resources and a number of requesters having a number of requests processing units, one associated with each one of the requesters, for receiving a resource type request signal from the associated requester, a number of grant processing units, one associated with each one of the resources, for monitoring a busy status signal from said associated resource, a common broadcast medium coupled to the number of request processing units and the grant processing units, and an arbiter for granting access to said common broadcast medium to one of the request processing units and the grant processing units using the common broadcast medium to control the coupling order between the requesters and the resources in a first come, first served manner.
摘要翻译：一种用于控制多个资源与具有多个请求处理单元的请求者之间的耦合顺序的仲裁机制，一个与请求者中的每一个相关联的请求者，用于从相关联的请求者接收资源类型请求信号，多个授权处理单元，与每个资源相关联的一个，用于监视来自所述相关资源的繁忙状态信号;耦合到所述多个请求处理单元和所述授权处理单元的公共广播媒体;以及仲裁器，用于授予对所述公共广播介质到请求处理单元之一以及使用公共广播介质的授权处理单元，以先到先得的方式控制请求者与资源之间的耦合顺序。

9. 发明授权

US6072772A Method for providing bandwidth and delay guarantees in a crossbar switch with speedup 失效
标题翻译：在具有加速功能的交叉开关中提供带宽和延迟保证的方法
公开(公告)号：US6072772A
公开(公告)日：2000-06-06
申请号：US005738
申请日：1998-01-12
申请人： Anna Charny , Pattabhiraman Krishna , Naimish Patel , Robert J. Simcoe
发明人： Anna Charny , Pattabhiraman Krishna , Naimish Patel , Robert J. Simcoe
IPC分类号： H04L12/70 , H04L12/931 , H04L12/933 , H04L12/935 , H04L12/937 , H04Q11/04 , G01R31/08
CPC分类号： H04L49/503 , H04L49/1576 , H04L49/205 , H04L49/254 , H04L49/3045 , H04L49/3081 , H04Q11/0478 , H04L2012/5649 , H04L2012/5679 , H04L2012/5683
摘要： An arbitration scheme for providing deterministic bandwidth and delay guarantees in an input-buffered crossbar switch with speedup S is presented. Within the framework of a crossbar architecture having a plurality of input channels and output channels, the arbitration scheme determines the sequence of fixed-size packet (or cell) transmissions between the inputs channels and outputs channels satisfying the constraint that only one cell can leave an input channel and enter an output channel per phase in such a way that the arbitration delay is bounded for each cell awaiting transmission at the input channel. If the fixed-sized packets result from fragmentation of variable size packets, the scheduling and arbitration scheme determines deterministic delay guarantees to the initial variable size packets (re-assembled at the output channel) as well.
摘要翻译：提出了一种用于在具有加速S的输入缓冲交叉开关中提供确定性带宽和延迟保证的仲裁方案。在具有多个输入通道和输出通道的交叉开关架构的框架内，仲裁方案确定输入通道之间的固定大小分组（或小区）传输的顺序，并输出满足只有一个单元可以离开输入通道，并以每个相位输入一个输出通道，使仲裁延迟对于等待输入通道传输的每个单元有界。如果固定大小的分组是由可变大小分组的分片引起的，则调度和仲裁方案也确定对初始可变大小分组的确定性延迟保证（在输出信道上重新组合）。

10. 发明授权

US4296335A High voltage standoff MOS driver circuitry 失效
标题翻译：高压对位MOS驱动电路
公开(公告)号：US4296335A
公开(公告)日：1981-10-20
申请号：US53300
申请日：1979-06-29
申请人： Robert J. Simcoe
发明人： Robert J. Simcoe
IPC分类号： H03K19/0185 , H02H9/00
CPC分类号： H03K19/018557 , H03K19/01855
摘要： MOS circuitry conducting constant current at high voltage comprises first, second and third depletion mode MOSFETs connected in a loop, with their gates joined at the junction of the second and third MOSFETs. A control circuit is coupled to the junction of the first and second MOSFETs. The drain of an enhancement mode fourth MOSFET is connected to the junction of the second and third MOSFETs while its source remains unconnected. With high voltage applied to the junction of the first and third MOSFETs, and with the control circuit essentially nonconductive, the fourth MOSFET experiences diode breakdown, thereby acting as a high voltage source which prevents gate oxide rupture on the first, second and third MOSFETs and causing the first and second MOSFETs to become nonconductive until the control circuit is again rendered conductive.
摘要翻译：在高电压下传导恒定电流的MOS电路包括以环路连接的第一，第二和第三耗尽型MOSFET，其栅极连接在第二和第三MOSFET的结。控制电路耦合到第一和第二MOSFET的结。增强型第四MOSFET的漏极连接到第二和第三MOSFET的结，而其源保持不连接。由于施加到第一和第三MOSFET的结的高电压并且与控制电路基本上不导通，所以第四MOSFET经历二极管击穿，由此用作高电压源，以防止第一，第二和第三MOSFET上的栅极氧化物破裂，以及导致第一和第二MOSFET变得不导通，直到控制电路再次导通。

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