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1. 发明授权

US08324107B2 Method for forming high density patterns 有权
标题翻译：形成高密度图案的方法
公开(公告)号：US08324107B2
公开(公告)日：2012-12-04
申请号：US12686602
申请日：2010-01-13
申请人： Baosuo Zhou , Gurtej S. Sandhu , Ardavan Niroomand
发明人： Baosuo Zhou , Gurtej S. Sandhu , Ardavan Niroomand
IPC分类号： H01L21/311
CPC分类号： H01L21/76885 , H01L21/0337 , H01L21/0338 , H01L21/76816
摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.
摘要翻译：公开了诸如涉及增加集成电路中的隔离特征的密度的方法。在一个或多个实施例中，提供了一种用于形成具有孤立特征图案的集成电路的方法，其具有比集成电路中的隔离特征的起始密度大2倍或更多倍的隔离特征的最终密度。该方法可以包括形成具有密度X的柱状图案，并且在柱之间形成孔的图案，孔的密度至少为X.可以选择性地去除柱，以形成至少具有密度的孔的图案 2X。在一些实施例中，插塞可以以空穴的图案形成，例如通过外延沉积在基板上，以便提供具有密度2X的柱状图案。在其他实施例中，孔的图案可以通过蚀刻转移到衬底。

2. 发明申请

US20090149026A1 METHOD FOR FORMING HIGH DENSITY PATTERNS 有权
标题翻译：形成高密度图案的方法
公开(公告)号：US20090149026A1
公开(公告)日：2009-06-11
申请号：US11952017
申请日：2007-12-06
申请人： Baosuo Zhou , Gurtej S. Sandhu , Ardavan Niroomand
发明人： Baosuo Zhou , Gurtej S. Sandhu , Ardavan Niroomand
IPC分类号： H01L21/311
CPC分类号： H01L21/76885 , H01L21/0337 , H01L21/0338 , H01L21/76816
摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.
摘要翻译：公开了诸如涉及增加集成电路中的隔离特征的密度的方法。在一个或多个实施例中，提供了一种用于形成具有孤立特征图案的集成电路的方法，其具有比集成电路中的隔离特征的起始密度大2倍或更多倍的隔离特征的最终密度。该方法可以包括形成具有密度X的柱状图案，并且在柱之间形成孔的图案，孔的密度至少为X.可以选择性地去除柱，以形成至少具有密度的孔的图案 2X。在一些实施例中，插塞可以以空穴的图案形成，例如通过外延沉积在基板上，以便提供具有密度2X的柱状图案。在其他实施例中，孔的图案可以通过蚀刻转移到衬底。

3. 发明申请

US20100112818A1 METHOD FOR FORMING HIGH DENSITY PATTERNS 有权
标题翻译：形成高密度图案的方法
公开(公告)号：US20100112818A1
公开(公告)日：2010-05-06
申请号：US12686602
申请日：2010-01-13
申请人： Baosuo Zhou , Gurtej S. Sandhu , Ardavan Niroomand
发明人： Baosuo Zhou , Gurtej S. Sandhu , Ardavan Niroomand
IPC分类号： H01L21/306 , H01L21/31
CPC分类号： H01L21/76885 , H01L21/0337 , H01L21/0338 , H01L21/76816
摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.
摘要翻译：公开了诸如涉及增加集成电路中的隔离特征的密度的方法。在一个或多个实施例中，提供了一种用于形成具有孤立特征图案的集成电路的方法，其具有比集成电路中的隔离特征的起始密度大2倍或更多倍的隔离特征的最终密度。该方法可以包括形成具有密度X的柱状图案，并且在柱之间形成孔的图案，孔的密度至少为X.可以选择性地去除柱，以形成至少具有密度的孔的图案 2X。在一些实施例中，插塞可以以空穴的图案形成，例如通过外延沉积在基板上，以便提供具有密度2X的柱状图案。在其他实施例中，孔的图案可以通过蚀刻转移到衬底。

4. 发明授权

US07659208B2 Method for forming high density patterns 有权
标题翻译：形成高密度图案的方法
公开(公告)号：US07659208B2
公开(公告)日：2010-02-09
申请号：US11952017
申请日：2007-12-06
申请人： Baosuo Zhou , Gurtej S. Sandhu , Ardavan Niroomand
发明人： Baosuo Zhou , Gurtej S. Sandhu , Ardavan Niroomand
IPC分类号： H01L21/311
CPC分类号： H01L21/76885 , H01L21/0337 , H01L21/0338 , H01L21/76816
摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.
摘要翻译：公开了诸如涉及增加集成电路中的隔离特征的密度的方法。在一个或多个实施例中，提供了一种用于形成具有孤立特征图案的集成电路的方法，其具有比集成电路中的隔离特征的起始密度大2倍或更多倍的隔离特征的最终密度。该方法可以包括形成具有密度X的柱状图案，并且在柱之间形成孔的图案，孔的密度至少为X.可以选择性地去除柱，以形成至少具有密度的孔的图案 2X。在一些实施例中，插塞可以以空穴的图案形成，例如通过外延沉积在基板上，以便提供具有密度2X的柱状图案。在其他实施例中，孔的图案可以通过蚀刻转移到衬底。

5. 发明授权

US08030217B2 Simplified pitch doubling process flow 有权
标题翻译：简化俯仰加倍流程
公开(公告)号：US08030217B2
公开(公告)日：2011-10-04
申请号：US12771951
申请日：2010-04-30
申请人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
发明人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
IPC分类号： H01L21/302
CPC分类号： H01L27/04 , H01L21/0338 , H01L21/3088 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.
摘要翻译：一种用于制造半导体器件的方法包括对一层光致抗蚀剂材料进行构图以形成多个心轴。该方法还包括通过原子层沉积（ALD）工艺在多个心轴上沉积氧化物材料。该方法还包括从暴露的水平表面各向异性地蚀刻氧化物材料。该方法还包括选择性地蚀刻光刻胶材料。

6. 发明授权

US07732343B2 Simplified pitch doubling process flow 有权
标题翻译：简化俯仰加倍流程
公开(公告)号：US07732343B2
公开(公告)日：2010-06-08
申请号：US11744074
申请日：2007-05-03
申请人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
发明人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
IPC分类号： H01L21/302
CPC分类号： H01L27/04 , H01L21/0338 , H01L21/3088 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.
摘要翻译：一种用于制造半导体器件的方法包括对一层光致抗蚀剂材料进行构图以形成多个心轴。该方法还包括通过原子层沉积（ALD）工艺在多个心轴上沉积氧化物材料。该方法还包括从暴露的水平表面各向异性地蚀刻氧化物材料。该方法还包括选择性地蚀刻光刻胶材料。

7. 发明授权

US07902074B2 Simplified pitch doubling process flow 有权
标题翻译：简化俯仰加倍流程
公开(公告)号：US07902074B2
公开(公告)日：2011-03-08
申请号：US11400603
申请日：2006-04-07
申请人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
发明人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
IPC分类号： H01L21/311
CPC分类号： H01L27/04 , H01L21/0338 , H01L21/3088 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region. The method further comprises depositing an oxide material over the plurality of mandrels and over a device peripheral region. The method further comprises forming a pattern of photoresist material over the oxide material in the device peripheral region. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces in the device array region. The method further comprises selectively etching photoresist material from the device array region and from the device peripheral region.
摘要翻译：一种用于制造半导体器件的方法包括将光致抗蚀剂材料层图案化以在器件阵列区域中形成多个心轴。该方法还包括在多个心轴上并在器件外围区域上沉积氧化物材料。该方法还包括在器件外围区域中的氧化物材料上形成光致抗蚀剂材料的图案。该方法还包括从器件阵列区域中暴露的水平表面各向异性地蚀刻氧化物材料。该方法还包括从器件阵列区域和器件外围区域选择性地蚀刻光致抗蚀剂材料。

8. 发明授权

US08852851B2 Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same 有权
标题翻译：在形成半导体器件期间使用交替间隔物沉积的减径技术及包括其的系统
公开(公告)号：US08852851B2
公开(公告)日：2014-10-07
申请号：US11484271
申请日：2006-07-10
申请人： Baosuo Zhou , Mirzafer K. Abatchev , Ardavan Niroomand , Paul A. Morgan , Shuang Meng , Joseph N. Greeley , Brian J. Coppa
发明人： Baosuo Zhou , Mirzafer K. Abatchev , Ardavan Niroomand , Paul A. Morgan , Shuang Meng , Joseph N. Greeley , Brian J. Coppa
IPC分类号： H01L21/033 , H01L21/308
CPC分类号： H01L21/30625 , H01L21/0335 , H01L21/0337 , H01L21/0338 , H01L21/30604 , H01L21/3086 , H01L21/3088 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
摘要翻译：图案化层的方法使用一系列自对准间隔物增加在初始图案化层上形成的特征的密度。提供待蚀刻的层，然后在待蚀刻的层上形成例如使用光学光刻形成的初始牺牲图案形成层。根据实施例，图案化层可以被修整，然后形成并蚀刻一系列间隔层。间隔层的数量及其目标尺寸取决于所需的特征密度增加。还描述了一种过程中半导体器件和电子系统。

9. 发明授权

US08338959B2 Simplified pitch doubling process flow 有权
标题翻译：简化俯仰加倍流程
公开(公告)号：US08338959B2
公开(公告)日：2012-12-25
申请号：US13229898
申请日：2011-09-12
申请人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
发明人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
IPC分类号： H01L23/48
CPC分类号： H01L27/04 , H01L21/0338 , H01L21/3088 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.
摘要翻译：一种用于制造半导体器件的方法包括对一层光致抗蚀剂材料进行构图以形成多个心轴。该方法还包括通过原子层沉积（ALD）工艺在多个心轴上沉积氧化物材料。该方法还包括从暴露的水平表面各向异性地蚀刻氧化物材料。该方法还包括选择性地蚀刻光刻胶材料。

10. 发明申请

US20110316114A1 SIMPLIFIED PITCH DOUBLING PROCESS FLOW 有权
标题翻译：简化的PITCH DOUBLING PROCESS FLOW
公开(公告)号：US20110316114A1
公开(公告)日：2011-12-29
申请号：US13229898
申请日：2011-09-12
申请人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
发明人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
IPC分类号： H01L27/06
CPC分类号： H01L27/04 , H01L21/0338 , H01L21/3088 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.
摘要翻译：一种用于制造半导体器件的方法包括对一层光致抗蚀剂材料进行构图以形成多个心轴。该方法还包括通过原子层沉积（ALD）工艺在多个心轴上沉积氧化物材料。该方法还包括从暴露的水平表面各向异性地蚀刻氧化物材料。该方法还包括选择性地蚀刻光刻胶材料。

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