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1. 发明授权

US07000226B2 Exception masking in binary translation 有权
公开(公告)号：US07000226B2
公开(公告)日：2006-02-14
申请号：US10038139
申请日：2002-01-02
申请人： Baiming Gao , Yun Wang , Yigal Zemach , Orna Etzion , Jianhui Li
发明人： Baiming Gao , Yun Wang , Yigal Zemach , Orna Etzion , Jianhui Li
IPC分类号： G06F9/45
CPC分类号： G06F9/4812 , G06F8/52
摘要： Mapping of exception masks between source and target architectures with different numbers of exception masks enables a binary translator to translate code from the source to the target architecture and to determine an appropriate state for the source architecture if an exception is raised when executing the translated code.

2. 发明授权

US07249350B2 Optimized translation of scalar type SIMD instructions into non-scalar SIMD instructions 有权
标题翻译：将标量型SIMD指令优化为非标量SIMD指令
公开(公告)号：US07249350B2
公开(公告)日：2007-07-24
申请号：US10259843
申请日：2002-09-30
申请人： Yun Wang , Orna Etzion
发明人： Yun Wang , Orna Etzion
IPC分类号： G06F9/45 , G06F15/00
CPC分类号： G06F8/52
摘要： An arrangement is provided for translating a plurality of scalar single instruction multiple data stream (SIMD) instructions into a plurality of optimized non-scalar SIMD instructions to be executed on a target architecture supporting only parallel SIMID instructions. After receiving a plurality of scalar SIiVLD instructions, translation from the scalar SIMD instructions to non-scalar SIMD instructions is performed. The translation is optimized so that the number of translated non-scalar SIMD instructions is minimized. The translated non-scalar SIIViD instructions are executed on a target architecture that supports only parallel SIMD instructions.
摘要翻译：提供了一种用于将多个标量单指令多数据流（SIMD）指令转换为要在仅支持并行SIMID指令的目标架构上执行的多个优化的非标量SIMD指令的布置。在接收到多个标量SIiVLD指令之后，执行从标量SIMD指令到非标量SIMD指令的转换。翻译被优化，使得翻译的非标量SIMD指令的数量被最小化。转换的非标量SIIViD指令在仅支持并行SIMD指令的目标架构上执行。

3. 发明申请

US20050149913A1 Apparatus and methods to optimize code in view of masking status of exceptions 审中-公开
标题翻译：鉴于异常的屏蔽状态，优化代码的装置和方法
公开(公告)号：US20050149913A1
公开(公告)日：2005-07-07
申请号：US10745642
申请日：2003-12-29
申请人： Yun Wang , Orna Etzion
发明人： Yun Wang , Orna Etzion
IPC分类号： G06F9/45
CPC分类号： G06F9/45516
摘要： A source binary code that complies with a source architecture is translated to a target binary code that complies with a target architecture. The target binary code includes a first target portion translated from a respective source portion of the source binary code. During execution of the target binary code on a processor that complies with a target architecture, it is determined whether to retranslate the source portion to produce a second target portion that is more optimized to the target architecture than the first target portion or to retranslate the source portion to produce a third target portion that is more optimized to the target architecture than the second target portion.
摘要翻译：符合源架构的源二进制代码被转换为符合目标架构的目标二进制代码。目标二进制码包括从源二进制码的相应源部分翻译的第一目标部分。在符合目标架构的处理器上执行目标二进制代码期间，确定是否重新传输源部分以产生比目标架构比第一目标部分更优化的第二目标部分或者重新传输源以产生比目标结构比第二目标部分更优化的第三目标部分。

4. 发明申请

US20100050165A1 METHODS AND APPARATUS TO SUPPORT MIXED-MODE EXECUTION WITHIN A SINGLE INSTRUCTION SET ARCHITECTURE PROCESS OF A VIRTUAL MACHINE 有权
标题翻译：在虚拟机的一个指令集建筑过程中支持混合模式执行的方法和装置
公开(公告)号：US20100050165A1
公开(公告)日：2010-02-25
申请号：US12613295
申请日：2009-11-05
申请人： Miaobo Chen , Qi Zhang , Eric Lin , Jianhui Li , Yun Wang
发明人： Miaobo Chen , Qi Zhang , Eric Lin , Jianhui Li , Yun Wang
IPC分类号： G06F9/44
CPC分类号： G06F9/45516
摘要： Methods and apparatus to support the execution of a managed application that is linked to a native library or application are disclosed. The disclosed methods and apparatus support a virtual machine that is associated with the same ISA as the executing platform, while the ISA of the native library or application is of a different ISA. The disclosed methods and apparatus also support the execution of a managed application that is linked with several native libraries or applications that are associated with several different ISAs respectively.
摘要翻译：公开了支持与本地库或应用相关联的被管理应用的执行的方法和装置。所公开的方法和装置支持与执行平台相同的ISA相关联的虚拟机，而本地库或应用的ISA是不同的ISA。所公开的方法和装置还支持与分别与若干不同的ISA相关联的几个本地库或应用链接的被管理应用的执行。

5. 发明授权

US07634768B2 Methods and apparatus to support mixed-mode execution within a single instruction set architecture process of a virtual machine 有权
标题翻译：在虚拟机的单个指令集架构进程中支持混合模式执行的方法和装置
公开(公告)号：US07634768B2
公开(公告)日：2009-12-15
申请号：US11059902
申请日：2005-02-17
申请人： Miaobo Chen , Qi Zhang , Eric Lin , Jianhui Li , Yun Wang
发明人： Miaobo Chen , Qi Zhang , Eric Lin , Jianhui Li , Yun Wang
IPC分类号： G06F9/44
CPC分类号： G06F9/45516
摘要： Methods and apparatus to support the execution of a managed application that is linked to a native library or application are disclosed. The disclosed methods and apparatus support a virtual machine that is associated with the same ISA as the executing platform, while the ISA of the native library or application is of a different ISA. The disclosed methods and apparatus also support the execution of a managed application that is linked with several native libraries or applications that are associated with several different ISAs respectively.
摘要翻译：公开了支持与本地库或应用相关联的被管理应用的执行的方法和装置。所公开的方法和装置支持与执行平台相同的ISA相关联的虚拟机，而本地库或应用的ISA是不同的ISA。所公开的方法和装置还支持与分别与若干不同的ISA相关联的几个本地库或应用链接的被管理应用的执行。

6. 发明申请

US20060184919A1 Methods and apparatus to support mixed-mode execution within a single instruction set architecture process of a virtual machine 有权
公开(公告)号：US20060184919A1
公开(公告)日：2006-08-17
申请号：US11059902
申请日：2005-02-17
申请人： Miaobo Chen , Qi Zhang , Eric Lin , Jianhui Li , Yun Wang
发明人： Miaobo Chen , Qi Zhang , Eric Lin , Jianhui Li , Yun Wang
IPC分类号： G06F9/44
CPC分类号： G06F9/45516
摘要： Methods and apparatus to support the execution of a managed application that is linked to a native library or application are disclosed. The disclosed methods and apparatus support a virtual machine that is associated with the same ISA as the executing platform, while the ISA of the native library or application is of a different ISA. The disclosed methods and apparatus also support the execution of a managed application that is linked with several native libraries or applications that are associated with several different ISAs respectively.

7. 发明授权

US08015557B2 Methods and apparatus to support mixed-mode execution within a single instruction set architecture process of a virtual machine 有权
标题翻译：在虚拟机的单个指令集架构进程中支持混合模式执行的方法和装置
公开(公告)号：US08015557B2
公开(公告)日：2011-09-06
申请号：US12613295
申请日：2009-11-05
申请人： Miaobo Chen , Qi Zhang , Eric Lin , Jianhui Li , Yun Wang
发明人： Miaobo Chen , Qi Zhang , Eric Lin , Jianhui Li , Yun Wang
IPC分类号： G06F9/44
CPC分类号： G06F9/45516
摘要： Methods and apparatus to support the execution of a managed application that is linked to a native library or application are disclosed. The disclosed methods and apparatus support a virtual machine that is associated with the same ISA as the executing platform, while the ISA of the native library or application is of a different ISA. The disclosed methods and apparatus also support the execution of a managed application that is linked with several native libraries or applications that are associated with several different ISAs respectively.
摘要翻译：公开了支持与本地库或应用相关联的被管理应用的执行的方法和装置。所公开的方法和装置支持与执行平台相同的ISA相关联的虚拟机，而本地库或应用的ISA是不同的ISA。所公开的方法和装置还支持与分别与若干不同的ISA相关联的几个本地库或应用链接的被管理应用的执行。

8. 发明申请

US20090106744A1 Compiling and translating method and apparatus 审中-公开
标题翻译：编译方法和装置
公开(公告)号：US20090106744A1
公开(公告)日：2009-04-23
申请号：US10576907
申请日：2005-08-05
申请人： Jianhui Li , Yun Wang , Bo Huang , Yongnian Le , Jiangning Liu , Jinyun Ye
发明人： Jianhui Li , Yun Wang , Bo Huang , Yongnian Le , Jiangning Liu , Jinyun Ye
IPC分类号： G06F9/45
CPC分类号： G06F8/447
摘要： Methods and apparatus are described to compile and translate source code. In some embodiments, source code is compiled into source binary code for a source platform; an annotation section associated with the source binary code is generated, wherein the annotation section comprises an annotation for a scope, the scope comprising at least one block of the source binary code having at least one attribute to aid a translator optimization. If the scope comprises a plurality of blocks, the blocks have consecutive addresses with each other and have the at least one attribute in common. In the embodiments, the source binary code is further translated into target binary code for a target platform by utilizing the annotation section.
摘要翻译：描述了编译和翻译源代码的方法和设备。在一些实施例中，源代码被编译为源平台的源二进制代码; 生成与源二进制代码相关联的注释部分，其中注释部分包括范围的注释，所述范围包括具有至少一个属性的源二进制代码的至少一个块以辅助翻译器优化。如果范围包括多个块，则这些块具有彼此的连续地址并且具有共同的至少一个属性。在实施例中，源二进制码通过利用注释部分进一步转换为目标平台的目标二进制代码。

9. 发明授权

US08779407B2 Multifunctional electrode 有权
公开(公告)号：US08779407B2
公开(公告)日：2014-07-15
申请号：US13367662
申请日：2012-02-07
申请人： Hieu Pham , Vidyut Gopal , Imran Hashim , Dipankar Pramanik , Yun Wang , Hong Sheng Yang
发明人： Hieu Pham , Vidyut Gopal , Imran Hashim , Dipankar Pramanik , Yun Wang , Hong Sheng Yang
IPC分类号： H01L29/02
CPC分类号： C23C14/345 , C23C14/0042 , C23C14/0641 , C23C14/083 , C23C14/225 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1616 , H01L45/1625
摘要： A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 Ωcm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.

10. 发明授权

US08683420B2 Method and system of improved reliability testing 有权
标题翻译：改进可靠性测试方法和系统
公开(公告)号：US08683420B2
公开(公告)日：2014-03-25
申请号：US12948257
申请日：2010-11-17
申请人： Yun Wang , Tony P. Chiang , Ryan Clarke , Chi-I Lang , Yoram Schwarz
发明人： Yun Wang , Tony P. Chiang , Ryan Clarke , Chi-I Lang , Yoram Schwarz
IPC分类号： G06F17/50
CPC分类号： H01L22/14
摘要： A method and system of improved reliability testing includes providing a first substrate and a second substrate, each substrate comprising only a first metallization layer; processing regions on a first substrate by combinatorially varying at least one of materials, unit processes, and process sequences; performing a first reliability test on the processed regions on the first substrate to generate first results; processing regions on a second substrate in a combinatorial manner by varying at least one of materials, unit processes, and process sequences based on the first results of the first reliability test; performing a second reliability test on the processed regions on the second substrate to generate second results; and determining whether the first substrate and the second substrate meet a predetermined quality threshold based on the second results.
摘要翻译：改进的可靠性测试的方法和系统包括提供第一衬底和第二衬底，每个衬底仅包括第一金属化层; 通过组合地改变材料，单元过程和工艺顺序中的至少一个来处理第一衬底上的处理区域; 对所述第一基板上的所述经处理区域进行第一可靠性测试以产生第一结果; 基于第一可靠性测试的第一结果，通过改变材料，单元过程和过程序列中的至少一个来以组合的方式处理第二基板上的区域; 对所述第二基板上的所述经处理区域进行第二可靠性测试以产生第二结果; 以及基于所述第二结果来确定所述第一基板和所述第二基板是否满足预定质量阈值。

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