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1. 发明授权

US5978956A Five-error correction system 失效
公开(公告)号：US5978956A
公开(公告)日：1999-11-02
申请号：US984698
申请日：1997-12-03
申请人： Lih-Jyh Weng , Ba-Zhong Shen
发明人： Lih-Jyh Weng , Ba-Zhong Shen
IPC分类号： H03M13/15 , H03M13/00
CPC分类号： H03M13/6505 , H03M13/1575
摘要： An error correcting system transforms a degree-five error locator polynomial .sigma.(x) into the polynomial w(y)=y.sup.5 =b.sub.2 y.sup.2 +b.sub.1 y+b.sub.0, where b.sub.1 =0 or 1, and y=.sigma.(x), and determines the roots of .sigma.(x) based on the roots of w(y). The polynomial w(y) has (2.sup.M).sup.2 solutions over GF(2.sup.M), rather than (2.sup.M).sup.5 solutions, since for any solution with b.sub.2 =h.sub.2, b.sub.0 =h.sub.0 and b.sub.1 =1, there is no such solution with b.sub.2 =h.sub.2, b.sub.0 =h.sub.0 and b.sub.1 =0. Conversely, if there is such a solution with b.sub.1 =0 there are no such solutions with b.sub.1 =1. The system can thus use a table that has 2.sup.2M entries and is addressed by {b.sub.2, b.sub.0 }. The table produces roots y=r.sub.i, i=0, 1, 2, 3, 4, and the system then transforms the roots y=r.sub.i to the roots of .sigma.(x) by calculating x=.sigma..sup.-1 (y). To further reduce the overall table storage needs, the table may include in each entry four roots r.sub.i, i=0, 1, 2, 3, and the system then calculates the associated fifth root r.sub.4 by adding the stored roots. The size of the look-up table can be even further reduced by (i) segmenting the Galois Field (2.sup.M) into conjugate classes; (ii) determining which of the classes contain values of b.sub.0 that correspond to solutions of w(y) with five distinct roots; (iii) representing each of these classes, respectively, by a single value of b.sub.0 '=(b.sub.0).sup.2.spsp.k ; and (iv) including in the table for each class only those solutions that correspond to representative values of b.sub.0 '. The table then contains a relatively small number of sets of roots of each of the classes, with each set associated with a particular value of b.sub.2 '=b.sub.2.sup.2.spsp.k. The roots of w(y) are determined by finding the value of k that produces b.sub.0 ' and b.sub.2 ', entering the look-up table using {b.sub.0 ', b.sub.2 '}, raising the roots r.sub.i ' produced by the table to the power -2.sup.k to produce y=r.sub.i, and then transforming the result into the roots of .sigma.(x) by x=.sigma..sup.-1 (y).

2. 发明授权

US5948117A Modified Reed-Solomon error correction system using (W+i+1)-bit representations of symbols of GF(2.sup.w+i) 失效
标题翻译：使用GF（2w + i）的符号的（W + i + 1）位表示的修正Reed-Solomon纠错系统
公开(公告)号：US5948117A
公开(公告)日：1999-09-07
申请号：US786894
申请日：1997-01-23
申请人： Lih-Jyh Weng , Ba-Zhong Shen , Shih Mo
发明人： Lih-Jyh Weng , Ba-Zhong Shen , Shih Mo
IPC分类号： H03M13/00 , H03M13/15
CPC分类号： H03M13/151
摘要： An error correction system includes an encoder that uses a modified Reed-Solomon code to encode w-bit data symbols over GF(2.sup.w+i) and form a preliminary code with d-1 (w+i+1)-bit redundancy symbols. The preliminary code word is modified as necessary to set for each symbol a selected i bits to the same value as a corresponding i+1.sup.st bit. The preliminary code word also includes R pseudo redundancy symbols that are required for decoding the modified code word. The i+1 bits are then truncated from each of the code word symbols, to form a code word with w-bit symbols. The Galois Field GF(2.sup.w+i) is selected such that the elements of the field can be represented by (w+i+1)-bit symbols that are determined by a polynomial h(x) modulo an irreducible polynomial p(x), which isp(x)=x.sup.w+i +x.sup.w+i-1 + . . . +x.sup.1 +x.sup.0,with the polynomial h(x) representing a primitive element. The encoder uses the lower weight representations of the (w+i+1)-bit symbols and performs multiplication and raising the symbols to powers of 2.sup.i as combinations of cyclic shifts and permutations that are readily performed in hardware. A decoder decodes the code word as (w+i+1)-bit symbols to take advantage of the simplified multiplication and exponentiation operations.
摘要翻译：纠错系统包括使用经修改的里德 - 所罗门码对GF（2w + i）上的w位数据符号进行编码并用d-1（w + i + 1）位冗余符号形成初步码的编码器。根据需要修改初始码字，以将每个符号设置所选择的i位与相应的i + 1位相同的值。初始码字还包括用于解码修改的码字所需的R伪冗余符号。然后从每个码字符号中截断i + 1位，以形成具有w位符号的码字。选择伽罗瓦域GF（2w + i），使得场的元素可以由通过不可约多项式p（x）的多项式h（x）确定的（w + i + 1）位符号来表示，，其为p（x）= xw + i + xw + i-1 +。。。 + x1 + x0，多项式h（x）表示一个原始元素。编码器使用（w + i + 1）位符号的较低权重表示，并且执行乘法和将符号提升为2i的幂作为在硬件中容易执行的循环移位和排列的组合。解码器将码字解码为（w + i + 1）位符号，以利用简化的乘法运算和求幂运算。

3. 发明授权

US5901158A Error correction encoder/decoder 失效
标题翻译：纠错编码器/解码器
公开(公告)号：US5901158A
公开(公告)日：1999-05-04
申请号：US837752
申请日：1997-04-22
申请人： Lih-Jyh Weng , Ba-Zhong Shen , Shih Mo
发明人： Lih-Jyh Weng , Ba-Zhong Shen , Shih Mo
IPC分类号： G06F11/10 , G11B20/18 , H03M13/15 , H03M13/00
CPC分类号： G06F11/1008 , H03M13/151 , G11B20/1809
摘要： The encoder/decoder system uses encoder hardware to encode data symbols and form a data code word. To decode, the system uses the same encoder hardware to determine a residue r(x), i.e. ##EQU1## where C.sub.r (x) is the retrieved code word and g(x) is the generator polynomial. If the residue is all zeros, the ECC code word is error-free and the system need not calculate the error syndrome. If the residue is non-zero, the encoder hardware is used, with various switches in different settings, to include certain multipliers in and exclude other multipliers from the further decoding operations of encoding the residue symbols to produce partial error syndromes that are the coefficients of the error syndrome polynomial.
摘要翻译：编码器/解码器系统使用编码器硬件对数据符号进行编码并形成数据码字。为了解码，系统使用相同的编码器硬件来确定残差r（x），即，其中Cr（x）是检索的码字，g（x）是生成多项式。如果残差全为零，则ECC代码字是无错误的，并且系统不需要计算错误综合征。如果残差不为零，则使用编码器硬件，其中不同设置中的各种交换机将特定的乘法器包含在其中并且排除其他乘法器以及对残差码元进行编码的另外的解码操作，以产生作为系数的部分误差综合征误差多项式。

4. 发明授权

US06493845B1 Parallel input output combined system for producing error correction code redundancy symbols and error syndromes 失效
标题翻译：并行输入输出组合系统，用于产生纠错码冗余符号和误差综合征
公开(公告)号：US06493845B1
公开(公告)日：2002-12-10
申请号：US09337122
申请日：1999-06-21
申请人： Ba-Zhong Shen , Lih-Jyh Weng , Diana L. Langer
发明人： Ba-Zhong Shen , Lih-Jyh Weng , Diana L. Langer
IPC分类号： H03M1300
CPC分类号： H03M13/6561 , H03M13/1515 , H03M13/158 , H03M13/6575
摘要： A parallel input/output combined encoding and syndrome generating system encodes two information symbols per clock cycle, and thereafter, produces two redundancy symbols per clock cycle. For an n-symbol code word with 2k information symbols cn−1, to cn−2k, the symbols cn−1, cn−3, cn−5 . . . are supplied, in turn, to a first input line while the symbols cn−2, cn−4, cn−6, . . . are supplied, in turn, to a second input line. In a first clock cycle, the symbol cn−1 is combined with the contents of the R registers, where R is the number of redundancy symbols, and the contents are multiplied by the respective roots of the generator polynomial. The products then are combined with the paired symbol cn−2 and the resulting sums are multiplied also by the roots of the generator polynomial. These products are then summed in a chain of R adders and the respective registers are appropriately updated with the results of the encoding of the two symbols. During the next clock cycle, the next pair of information symbols are encoded, with cn−3 supplied to the first input line and cn−4 supplied to the second input line, and so forth. During the kth clock cycle, when the last of the pairs of information symbols are being encoded, the system produces the first two redundancy symbols. The first redundancy symbol is the update value for the last register rR−1, and the system then manipulates the update value, to produce the second redundancy symbol in the same clock cycle. The pair of redundancy symbols are next fed back to the two input lines and encoded, as discussed above. For decoding, the chain of R feedback adders is broken, and each set of adders and multipliers operates separately to update the associated register with the results of the manipulation of two code word symbols per clock cycle.
摘要翻译：并行输入/输出组合编码和校正子生成系统每个时钟周期对两个信息符号进行编码，此后每个时钟周期产生两个冗余符号。对于具有2k个信息符号cn-1，到cn-2k的符号cn-1，cn-3，cn-5的n符号码字。。。依次被提供给第一输入线，而符号cn-2，cn-4，cn-6，...，。。依次被提供给第二输入线。在第一时钟周期中，符号cn-1与R寄存器的内容组合，其中R是冗余符号的数量，并且内容与生成多项式的各个根相乘。然后，产品与配对符号cn-2组合，并且所得到的和也乘以生成多项式的根。然后将这些产品加在R加法器链中，并且用两个符号的编码结果适当地更新相应的寄存器。在下一个时钟周期中，下一对信息符号被编码，cn-3被提供给第一输入线，cn-4被提供给第二输入线，等等。在第k个时钟周期期间，当最后一对信息符号被编码时，系统产生前两个冗余符号。第一冗余符号是最后一个寄存器rR-1的更新值，然后系统操作更新值，以在相同的时钟周期产生第二个冗余符号。如上所述，该对冗余符号被反馈到两条输入线并进行编码。对于解码，R反馈加法器的链路被破坏，并且每组加法器和乘法器单独操作以更新相关联的寄存器与每个时钟周期对两个码字符号的操纵的结果。

5. 发明授权

US06343367B1 Error correction system for five or more errors 有权
标题翻译：纠错系统出现五个或更多错误
公开(公告)号：US06343367B1
公开(公告)日：2002-01-29
申请号：US09277785
申请日：1999-03-29
申请人： Ba-Zhong Shen , Lih-Jyh Weng
发明人： Ba-Zhong Shen , Lih-Jyh Weng
IPC分类号： H03M1300
CPC分类号： H03M13/152 , H03M13/1515 , H03M13/158
摘要： An error correcting system for correcting “t” errors over GF(2m), where t is even and preferably greater than or equal to six, transforms the t-degree error locator polynomial c(x) into a polynomial t(x) in which at−1≈0, where ai is the coefficient of the xi term of the error locator polynomial and Tr(at−1)=1, where Tr(ai) is the trace of ai. The polynomial t(x) is factored into two factors, namely, one factor that is the greatest common divisor of t(x) and S ⁡ ( x ) = ∑ i = 0 m - 1 ⁢ x 2 i , and a second factor that is the greatest common divisor of t(x) and S(x)+1. The system determines the greatest common divisor of the polynomial and S(x) in two steps, first iteratively determining a residue R(x)≡S(x)mod t(x), and then calculating the greatest common divisor of t(x) and the lower-degree R(x). The system produces two factors of t(x), namely, g(x)=gcd(t(x), R(x)) and h ⁡ ( x ) = t ⁡ ( x ) g ⁡ ( x ) , and then determines the roots of the factors and transforms these roots into the roots of the error locator polynomial or, as necessary, continues factoring into factors of lower degree before determining the roots. When “t” is odd, the system represents the roots ri of the error locator polynomial as a linear combination of ri,k&bgr;k for k=0,1 . . . m−1, where ri,k&egr;GF(2) and &bgr;k is an element of a dual basis for GF(2m) over GF(2), and Tr(&agr;j&bgr;k) equals one when j=k and equals zero when jk. The rootsri are then ri=ri,0&bgr;0+ri,1&bgr;1+ . . . +ri,m−1&bgr;m−1 and Tr ⁡ ( α j ⁢ r i ) = ∑ k = 0 m - 1 ⁢ r i , k ⁢ Tr ⁡ ( α j ⁢ β k ) = r i , j The system next determines the greatest common divisor of the polynomial and S(&agr;jx) by iteratively determining Rj(x)≡S(&agr;jx)mod c(x), and then determining the greatest common divisor of c(x) and Rj(x). The system next determines two factors of c(x) as g(x)=gcd(c(x), Rj(x)) and h ⁡ ( x ) = t ⁡ ( x ) g ⁡ ( x ) and finds the roots of the two factors.
摘要翻译：用于校正GF（2m）上的“t”误差的纠错系统，其中t为偶数，优选大于或等于6，将t度误差定位多项式c（x）转换为多项式t（x），其中 at-1≈0，其中ai是误差定位多项式的xi项的系数，Tr（at-1）= 1，其中Tr（ai）是ai的轨迹。多项式t（x）被分解为两个因素，即作为t（x）的最大公约数的一个因子，以及作为t（x）和S（x）+1的最大公约数的第二因子。系统在两个步骤中确定多项式和S（x）的最大公约数，首先迭代确定残差R（x）= S（x）mod t（x），然后计算t（x）的最大公约数）和较低等级R（x）。系统产生t（x）的两个因子，即g（x）= gcd（t（x），R（x）），然后确定因子的根，并将这些根变换到误差定位多项式的根或者根据需要在确定根源之前继续考虑到较低程度的因素。当“t”为奇数时，系统将误差定位多项式的根ri代表为k = 0,1的ri，kbetak的线性组合。。。 m-1，其中ri，kepsiGF（2）和betak是在GF（2）上的GF（2m）的双重基础的元素，并且当j = k时Tr（alphajbetak）等于1，并且当jk等于零时。然后，系统然后系统通过迭代确定Rj（x）= S（alphajx）mod c（x）来确定多项式和S（alphajx）的最大公约数，然后确定c（x）的最大公约数和 Rj（x）。系统接下来将c（x）的两个因子确定为g（x）= gcd（c（x），Rj（x）），并找出两个因素的根源。

6. 发明授权

US06199188B1 System for finding roots of degree three and degree four error locator polynomials over GF(2M) 有权
标题翻译：在GF（2M）上找到三度和四度误差定位多项式的根的系统
公开(公告)号：US06199188B1
公开(公告)日：2001-03-06
申请号：US09521518
申请日：2000-03-08
申请人： Ba-Zhong Shen , Lih-Jyh Weng
发明人： Ba-Zhong Shen , Lih-Jyh Weng
IPC分类号： H03M1300
CPC分类号： H03M13/1545 , H03M13/158
摘要： A system determines the locations of four errors in a code word over GF(2m), for any m, by transforming a degree-four error locator polynomial &sgr;(x) ultimately into two quadratic equations, finding the solutions of these equations, and from these solutions determining the roots of the error locator polynomial. The system first manipulates the degree-four error locator polynomial into a polynomial &thgr;(y) that has a coefficient of zero for the degree-three term. The system then factors this polynomial into two degree-two factors with four unknown variables. The system expands the factors and represents the coefficients of &thgr;(y) as expressions that include the four unknown variables, and manipulates the expressions to produce a degree-three polynomial with only one of the unknown variables. The system next solves for that variable by finding a root of the degree-three polynomial in GF(2m) if the field is an even-bit field or in an even-bit extension of GF(2m) if the field is an odd-bit field. The system then substitutes the root into the expressions for the coefficients of &thgr;(y) and produces a degree-two expression is with the remaining unknown variables. The system finds the roots of this expression, substitutes these values into the factors of&thgr;(y), and sets the factors equal to zero to produce two quadratic equations. The system then solves the equations to produce the roots of&thgr;(y), and from these solutions determines the roots of the degree-four error locator polynomial.
摘要翻译：系统通过将四度误差定位多项式西格玛（x）最终转换成两个二次方程，找出这些方程的解，并从...中求出GF（2m）中的码字中的四个误差的位置，对于任何m，这些解决方案确定了误差定位多项式的根。系统首先将四度误差定位多项式操作为三度项的系数为零的多项式theta（y）。然后系统将该多项式归因为具有四个未知变量的二度二因子。系统扩展因子，并将theta（y）的系数表示为包含四个未知变量的表达式，并且操纵表达式以产生仅具有一个未知变量的三阶多项式。如果该场是偶数位域，或者GF（2m）的偶数位扩展，则该系统接下来通过找到GF（2m）中的三度三项式的根，来解决该变量，位字段。然后，系统将根代入theta（y）的系数的表达式，并产生二度表达式与其余未知变量。该系统找到这个表达式的根源，将这些值代入theta（y）的因子，并将因子设置为零以产生两个二次方程。然后，系统解决方程以产生theta（y）的根，并且从这些解决方案确定四度误差定位多项式的根。

7. 发明授权

US6044389A System for computing the multiplicative inverse of a field element for galois fields without using tables 失效
公开(公告)号：US6044389A
公开(公告)日：2000-03-28
申请号：US999038
申请日：1997-12-29
申请人： Lih-Jyh Weng , Ba-Zhong Shen
发明人： Lih-Jyh Weng , Ba-Zhong Shen
IPC分类号： G06F7/72 , G06F7/00
CPC分类号： G06F7/726
摘要： A system for determining the multiplicative inverse of an element of GF(2.sup.m) by raising the element to the power 2.sup.m -2. The system may raise the element .alpha..sup.j to the power 2.sup.m -2 by repeatedly multiplying the element by itself 2.sup.m -3 times. Alternatively, the system may produce the exponent 2.sup.m -2 as the sum of:2.sup.m-1 +2.sup.m-2 + . . . +2.sup.3 +2.sup.2 +2.sup.1and thus (.alpha..sup.j).sub.2.spsp.m.sup.-2 as(.alpha..sup.j).sup.2.spsp.m.sup.-1 *(.alpha..sup.j).sup.2.spsp.m.sup.-2 * . . . *(.alpha..sup.j).sup.2.spsp.3 *(.alpha..sup.j).sup.2.spsp.2 *(.alpha..sup.j).sup.2The system may iteratively square .alpha..sup.j to produce the various factors (.alpha..sup.j).sup.2.spsp.m.sup.-1 *(.alpha..sup.j).sup.2.spsp.m.sup.-2 * . . . *(.alpha..sup.j).sup.2 and, using a single multiplier, multiply and accumulate the results. Alternatively, the system may use a plurality of circuits operating in parallel and simultaneously raise the element .alpha..sup.j to the powers 2.sup.m-1, 2.sup.m-2 . . . 2 to produce the factors, and use a plurality of tiered multipliers to multiply the factors together. The system may instead raise the element .alpha..sup.j to the power 2.sup.m -2 using a relatively small number of "stages," by producing the exponent 2.sup.m -1 as a combination of various products and sums. The products are implemented by raising the appropriate Galois Field elements to powers of 2 and the sums are implement by multiplying elements together. The system implemented in this manner includes in a first stage circuits that in parallel raise the element .alpha..sup.j to various powers of 2; in a second stage multipliers that selectively combine the results produced by the first stage; and in succeeding stages circuits that raise selected products produced in the preceding stages to various powers of 2 and multipliers that selectively combine the elements produced in the preceding stages. For those GF(2.sup.m) in which the elements can be represented by (m+1)-bit symbols, the system raises elements to powers of two by permuting the bits of the (m+1)-bit symbols and multiplies two elements together as (m+1)-bit symbols by cyclically shifting copies of one of the (m+1)-bit symbols, exclusive-OR'ing the bits of the shifted copies with the bits of the other (m+1)-bit symbol and summing the results.

8. 发明授权

US5999959A Galois field multiplier 失效
标题翻译：伽罗瓦域倍增器
公开(公告)号：US5999959A
公开(公告)日：1999-12-07
申请号：US25419
申请日：1998-02-18
申请人： Lih-Jyh Weng , Ba-Zhong Shen , Diana Langer
发明人： Lih-Jyh Weng , Ba-Zhong Shen , Diana Langer
IPC分类号： G06F7/72 , G06F7/00
CPC分类号： G06F7/724
摘要： A Galois field multiplier for GF(2.sup.n), with n=2m, multiplies two n-bit polynomials to produce a(x)*b(x)=a(x)b(x) mod g(x), where g(x) is a generator polynomial for the Galois field and "*" represents multiplication over the Galois field, by treating each polynomial as the sum of two m-bit polynomials:a(x)=a.sub.H (x)x.sup.m +a.sub.L (x) and b(x)=b.sub.H (x)x.sup.m +b.sub.L (x),witha.sub.H (x)x.sup.m =[a.sub.n-1 x.sup.(n-1)-m +a.sub.n-2 x.sup.(n-2)-m + . . . +a.sub.m+1 x.sup.(m+1)-m +a.sub.m ]x.sup.ma.sub.L (x)=a.sub.m-1 x.sup.m-1 +a.sub.m-2 x.sup.m-2 + . . . +a.sub.2 x.sup.2 +a.sub.1 x+a.sub.0and b.sub.H and b.sub.L having corresponding terms. Multiplying the two polynomials then becomes:a(x)*b(x)=(a.sub.H (x)x.sup.m +a.sub.L (x))*(b.sub.H (x)x.sup.m +b.sub.L (x))=[(a.sub.H (x)b(x).sub.H)x.sup.m mod g(x)+(b.sub.H (x)a.sub.L (x)+a.sub.L (x)b.sub.L (x))]x.sup.m mod g(x)+a.sub.L (x)b.sub.L (x).The Galois field multiplier produces four degree-(n-2) polynomial products, namely, a.sub.H (x)b.sub.H (x)=V.sub.3 ; b.sub.H (x)a.sub.L (x)=V.sub.2 ; a.sub.H (x)b.sub.L (x)=V.sub.1 ; and a.sub.L (x)b.sub.L (x)=V.sub.0, in parallel in four m-bit polynomial multipliers. Next, a modulo subsystem multiplies V.sub.3 by x.sup.m and performs a modulo g(x) operation on the product V.sub.3 x.sup.m by treating V.sub.3 as V.sub.3H x.sup.m +V.sub.3L, with V.sub.3H including as a leading term 0x.sup.n-1. The modulo operation is performed by appropriately cyclically shifting (m-(k-2)) versions of an n-bit symbol that consists of the coefficients of V.sub.3H followed by m zeros, summing the results and adding the sum to an n-bit symbol that consists of the coefficients of V.sub.3L, V.sub.3H. The Galois field multiplier for GF(2.sup.n) with n=2m+1 operates in essentially the same manner, with a.sub.L and b.sub.L each including m+1 terms.
摘要翻译： GF（2n）的伽罗瓦域乘法器，n = 2m，乘以两个n位多项式以产生a（x）* b（x）= a（x）b（x）mod g（x），其中g（ x）是伽罗瓦域的生成多项式，“*”表示伽罗瓦域上的乘积，通过将每个多项式作为两个m位多项式的和来处理：a（x）= aH（x）xm + aL（x）和b（x）= bH（x）xm + bL（x），其中h（x）xm = [an-1x（n-1）-m + an-2x（n-2）-m + 。。 + am + 1x（m + 1）-m + am] xmaL（x）= am-1xm-1 + am-2xm-2 +。。。 + a2x2 + a1x + a0和bH和bL具有相应的项。乘以两个多项式然后变为：a（x）* b（x）=（aH（x）xm + aL（x））*（bH（x）xm + bL（x））= [（aH（x）（x）H）xmmod g（x）+（bH（x）aL（x）+ aL（x）bL（x））] xmmod g（x）+ aL（x）产生四度 - （n-2）多项式积，即aH（x）bH（x）= V3; bH（x）aL（x）= V2; aH（x）bL（x）= V1; 和aL（x）bL（x）= V0，并联在四个m位多项式乘法器中。接下来，模子系统将V3乘以xm，并通过将V3视为V3Hxm + V3L，对产品V3xm执行模g（x）操作，V3H包括作为领先项0xn-1。通过适当循环移位（m-（k-2））版本的n位符号来执行模运算，该n位符号包括V3H的系数，随后是m个零，对结果求和并将和加到n位符号由V3L，V3H的系数组成。具有n = 2m + 1的GF（2n）的伽罗瓦域乘法器基本上以相同的方式操作，其中aL和bL各自包括m + 1项。

9. 发明授权

US5889794A Two-level error correction encoder 失效
标题翻译：两级纠错编码器
公开(公告)号：US5889794A
公开(公告)日：1999-03-30
申请号：US940187
申请日：1997-09-30
申请人： Shih Mo , Stanley Chang , Lih-Jyh Weng , Ba-Zhong Shen
发明人： Shih Mo , Stanley Chang , Lih-Jyh Weng , Ba-Zhong Shen
IPC分类号： H03M13/00 , H03M13/15
CPC分类号： H03M13/15 , H03M13/00
摘要： A two-level error correction encoder encodes m-bit data symbols in a first level of encoding in accordance with a distance d ECC over GF(2.sup.m+i) to produce (m+i)-bit ECC redundancy symbols and, during a second level of encoding, both modifies the set of ECC redundancy symbols, as necessary, to set i selected bits in each symbol in a predetermined truncation pattern and appends to the set of ECC symbols one or more pseudo redundancy symbols. The encoder includes d-1 Galois Field multipliers, and d-1 associated redundancy-symbol registers and an ECC symbol modifier lookup table that has stored therein information that the encoder uses during the second level of encoding. After the first level of encoding, the d-1 registers contain the (m+i)-bit ECC redundancy symbols. These symbols are used to enter the look-up table and select information that the encoder then encodes along with the ECC redundancy symbols, to produce the modified ECC redundancy symbols and append thereto one or more pseudo redundancy symbols. As the ECC redundancy symbols are modified, the encoding system removes them from the two-level encoder and appends them to the data. The last symbol(s) removed from the encoder and appended to the data are the one or more pseudo redundancy symbols. The system then truncates the i-bit pattern from each of the redundancy symbols to produce, at the end of the two-level encoding operation, a data code word that includes the m-bit data symbols, the m-bit modified ECC redundancy symbols and one or more m-bit pseudo redundancy symbols.
摘要翻译：两级纠错编码器根据GF（2m + i）上的距离d ECC编码第一编码级别的m位数据符号，以产生（m + i）位ECC冗余符号，并且在第二级根据需要，根据需要修改ECC冗余符号集合，以预定的截断模式设置每个符号中的所选择的比特，并将附加到ECC符号的集合中的一个或多个伪冗余符号。编码器包括d-1伽罗瓦域乘法器和d-1相关联的冗余符号寄存器和ECC符号修改器查找表，其中存储编码器在第二编码级别期间使用的信息。在第一级编码之后，d-1寄存器包含（m + i）位ECC冗余符号。这些符号用于输入查找表并选择编码器随后与ECC冗余符号一起被编码的信息，以产生经修改的ECC冗余符号并附加到一个或多个伪冗余符号。随着ECC冗余符号的修改，编码系统将它们从二级编码器中删除，并将它们附加到数据中。从编码器移除并附加到数据的最后一个符号是一个或多个伪冗余符号。系统然后从每个冗余符号中截断i比特模式，以在两级编码操作结束时产生包括m比特数据符号的数据码字，m位修改的ECC冗余符号和一个或多个m位伪冗余符号。

10. 发明授权

US06701336B1 Shared galois field multiplier 失效
标题翻译：共享伽罗瓦域倍增器
公开(公告)号：US06701336B1
公开(公告)日：2004-03-02
申请号：US09439774
申请日：1999-11-12
申请人： Ba-Zhong Shen , Lih-Jyh Weng
发明人： Ba-Zhong Shen , Lih-Jyh Weng
IPC分类号： G06F700
CPC分类号： G06F7/724 , G06F2207/382
摘要： Two types of shared-field multipliers for performing multiplications on field elements of different sizes are presented. One type uses a “cyclic” Galois field GF(2m), that is, a Galois field GF(2m) generated by an irreducible polynomial xm+xm−1+xm−2+ . . . +x+1, and the other type uses a composite field structure. Each shared-field multiplier includes computation circuitry for receiving field elements as inputs, the computation circuitry being responsive to a control signal to perform computations based on the inputs having a first size to produce an output of the first size, or to perform computations based on the inputs having a second, different size to produce an output of the second size.
摘要翻译：提出了用于对不同大小的场元素执行乘法的两种类型的共享场乘法器。一种类型使用“循环”伽罗瓦域GF（2m），即由不可约多项式xm + x + x +。。。 + x + 1，另一种类型使用复合字段结构。每个共享场乘法器包括用于接收场元素作为输入的计算电路，所述计算电路响应于控制信号执行基于具有第一大小的输入的计算，以产生第一大小的输出，或者基于所述输入具有第二不同尺寸以产生所述第二尺寸的输出。

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