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1. 发明专利

DE112012007115T5 Wahlweise Logikprozessor-Zählung und Typauswahl für eine gegebene Arbeitsbelastung basierend auf Wärme- und Leistungsbudget-Einschränkungen der Plattform 未知
公开(公告)号：DE112012007115T5
公开(公告)日：2015-08-20
申请号：DE112012007115
申请日：2012-12-28
申请人： BRETT PAUL , FENGER RUSSELL J , GORBATOV EUGENE , HAHN SCOTT D , INTEL CORP , KHANNA GAURAV , KOUFATY DAVID A , NAIK MISHALI , NARVAEZ PAOLO , NAVEH ALON , PRABHAKARAN ABIRAMI , SODHI INDER M , SRINIVASA GANAPATI N , SUBBAREDDY DHEERAJ R , WEISSMANN ELIEZER
发明人： KOUFATY DAVID A , SODHI INDER M , WEISSMANN ELIEZER , GORBATOV EUGENE , SRINIVASA GANAPATI N , PRABHAKARAN ABIRAMI , BRETT PAUL , SUBBAREDDY DHEERAJ R , HAHN SCOTT D , NAIK MISHALI , NARVAEZ PAOLO , NAVEH ALON , KHANNA GAURAV , FENGER RUSSELL J
IPC分类号： G06F9/06 , G06F1/32 , G06F9/44 , G06F9/46
摘要： Ein Prozessor enthält mehrere physikalische Kerne, die mehrere logische Kerne verschiedener Kerntypen unterstützen, wobei die Kerntypen einen Typ großer Kerne und einen Typ kleiner Kerne enthalten. Eine Multi-Thread-Anwendung enthält mehrere Software-Threads, die von einem ersten Teilsatz logischer Kerne in einem ersten Zeitschlitz gleichzeitig ausgeführt werden. Basierend auf Daten, die aus Überwachen der Ausführung in dem ersten Zeitschlitz erfasst wurden, wählt der Prozessor einen zweiten Teilsatz logischer Kerne für gleichzeitige Ausführung der Software-Threads in einem zweiten Zeitschlitz aus. Jeder logische Kern in dem zweiten Teilsatz weist einen der Kerntypen auf, der mit den Charakteristika eines der Software-Threads übereinstimmt.

2. 发明申请

WO2006028652A8 COORDINATING IDLE STATE TRANSITIONS IN MULTI-CORE PROCESSORS 审中-公开
标题翻译：协调多核处理器中的空闲状态转换
公开(公告)号：WO2006028652A8
公开(公告)日：2006-04-27
申请号：PCT/US2005028699
申请日：2005-08-12
申请人： INTEL CORP , NAVEH ALON , MENDELSON AVI , ANATI ITTAI , WEISSMANN ELIEZER
发明人： NAVEH ALON , MENDELSON AVI , ANATI ITTAI , WEISSMANN ELIEZER
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3203 , Y02D10/171 , Y02D50/20
摘要： Systems and methods of managing processors provide for detecting a command at a core of a processor having a plurality of cores, where the command requests a transition of the core to an idle state. Power consumption of the core is managed based on the command and an idle state status of each of the plurality of cores.

3. 发明申请

WO2007024435A3 DYNAMIC MEMORY SIZING FOR POWER REDUCTION 审中-公开
标题翻译：动态内存缩减功能
公开(公告)号：WO2007024435A3
公开(公告)日：2007-11-29
申请号：PCT/US2006030201
申请日：2006-08-03
申请人： INTEL CORP , MANDELBLAT JULIUS , MEHALEL MOTY , MENDELSON AVI , NAVEH ALON
发明人： MANDELBLAT JULIUS , MEHALEL MOTY , MENDELSON AVI , NAVEH ALON
IPC分类号： G06F1/32 , G06F12/00
CPC分类号： G06F1/3275 , G06F1/3225 , G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： Systems and methods of dynamic memory for power reduction are described with respect to a memory with a coupled sleep device. In one embodiment, the operating requirements can reflect amount of memory required to perform commensurate operations. Memory power management logic is used to coordinate memory requirements with operating requirements. The sleep device is able to enable or disable the memory based on the requirements to reduce power consumption.
摘要翻译：关于具有耦合的睡眠设备的存储器描述用于功率降低的动态存储器的系统和方法。在一个实施例中，操作要求可以反映执行相应操作所需的内存量。内存电源管理逻辑用于根据操作要求来协调内存需求。睡眠设备能够基于要求来启用或禁用内存，以降低功耗。

4. 发明申请

WO2006073899A3 OPERATING POINT MANAGEMENT IN MULTI-CORE ARCHITECTURES 审中-公开
标题翻译：多核心架构中的操作点管理
公开(公告)号：WO2006073899A3
公开(公告)日：2007-01-04
申请号：PCT/US2005046847
申请日：2005-12-20
申请人： INTEL CORP , ROTEM EFRAIM , LAMDEN OREN , NAVEH ALON
发明人： ROTEM EFRAIM , LAMDEN OREN , NAVEH ALON
IPC分类号： G06F1/20
CPC分类号： G06F1/3287 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/324 , G06F1/3243 , G06F1/3275 , G06F1/3296 , G06F9/30083 , G06F9/3814 , G06F12/0862 , G06F12/0875 , G06F2212/452 , G06F2212/602 , Y02B60/1217 , Y02B60/1275 , Y02B60/1285 , Y02B60/32 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D50/20
摘要： Systems and methods of managing operating points provide for determining the number of active cores in a plurality of processor cores. A maximum operating point is selected for at least one of the active cores based on the number of active cores. In one embodiment, the number of active cores is determined by monitoring an ACPI processor power state signal of each of the plurality of cores.
摘要翻译：管理操作点的系统和方法提供用于确定多个处理器核心中的活动核心的数量。基于活动核心的数量，为至少一个活动核心选择最大工作点。在一个实施例中，通过监视多个核心中的每一个的ACPI处理器功率状态信号来确定活动核心的数量。

5. 发明申请

WO2006028652A3 Coordinating idle state transitions in multi-core processors 审中-公开
标题翻译：协调多核处理器中的空闲状态转换
公开(公告)号：WO2006028652A3
公开(公告)日：2006-07-06
申请号：PCT/US2005028699
申请日：2005-08-12
申请人： INTEL CORP , NAVEH ALON , MENDELSON AVI , ANATI ITTAI , WEISSMAN ELIEZER
发明人： NAVEH ALON , MENDELSON AVI , ANATI ITTAI , WEISSMAN ELIEZER
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3203 , Y02D10/171 , Y02D50/20
摘要： Systems and methods of managing processors provide for detecting a command at a core of a processor having a plurality of cores, where the command requests a transition of the core to an idle state. Power consumption of the core is managed based on the command and an idle state status of each of the plurality of cores.
摘要翻译：管理处理器的系统和方法提供用于检测具有多个核的处理器的核心处的命令，其中命令请求核到空闲状态。基于多个核心中的每一个的命令和空闲状态来管理核心的功耗。

6. 发明申请

WO2012129147A3 MANAGING POWER CONSUMPTION IN A MULTI-CORE PROCESSOR 审中-公开
标题翻译：在多核处理器中管理功耗
公开(公告)号：WO2012129147A3
公开(公告)日：2013-03-14
申请号：PCT/US2012029604
申请日：2012-03-19
申请人： INTEL CORP , FETZER ERIC , REIDLINGER REID J , SOLTIS DON , BOWHILL WILLIAM J , SHRIMALI SATISH , SISTLA KRISHNAKANTH , ROTEM EFRAIM , KUMAR RAKESH , GARG VIVEK , NAVEH ALON , SHARMA LOKESH
发明人： FETZER ERIC , REIDLINGER REID J , SOLTIS DON , BOWHILL WILLIAM J , SHRIMALI SATISH , SISTLA KRISHNAKANTH , ROTEM EFRAIM , KUMAR RAKESH , GARG VIVEK , NAVEH ALON , SHARMA LOKESH
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/324 , Y02B60/1217 , Y02B60/1285 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.
摘要翻译：处理器可以包括核心和无孔区域。可以通过控制处理器的Cdyn来控制核心区域消耗的功率，使得Cdyn处于可允许的Cdyn值内，而不管应用程序是否被核心区域处理。电源管理技术包括测量数字活动因素（DAF），监控架构和数据活动级别，以及通过基于活动级别来限制指令来控制功耗。作为节流指令的结果，节流可以在第3垂直和热设计点（TDP）中实现。此外，通过改变提供给无孔区域的参考电压VR和VP，可以减少核心区域处于深功率节省状态时由无孔区域消耗的空闲功率。结果，可以减少由无孔区域消耗的空闲功率。

7. 发明申请

WO2009045937A2 SYSTEMS AND METHODS FOR VOLTAGE REGULATOR COMMUNICATION 审中-公开
标题翻译：用于电压调节器通信的系统和方法
公开(公告)号：WO2009045937A2
公开(公告)日：2009-04-09
申请号：PCT/US2008078056
申请日：2008-09-29
申请人： INTEL CORP , RODRIGUEZ JORGE , NAVEH ALON , SCHWARZBAND GIL , MA HUNG-PIAO , RUSU STEFAN , HERMERDING JAMES G , SANTOS ISHMAEL R , DIBENE II JOSEPH T , STANFORD EDWARD
发明人： RODRIGUEZ JORGE , NAVEH ALON , SCHWARZBAND GIL , MA HUNG-PIAO , RUSU STEFAN , HERMERDING JAMES G , SANTOS ISHMAEL R , DIBENE II JOSEPH T , STANFORD EDWARD
IPC分类号： G05F1/10
CPC分类号： G06F1/26
摘要： Systems and method for providing a regulated voltage supply to an integrated circuit. In an embodiment of the invention, a voltage regulator in a system provides an integrated circuit in the system with information related to the voltage regulator providing a supply voltage to the integrated circuit. In another embodiment of the invention, the integrated circuit makes determinations about the operating characteristic of the system using information from the voltage regulator.
摘要翻译：为集成电路提供稳压电源的系统和方法。在本发明的一个实施例中，系统中的电压调节器为系统中的集成电路提供与电压调节器相关的信息，该电压调节器向集成电路提供电源电压。在本发明的另一个实施例中，集成电路使用来自电压调节器的信息来确定系统的工作特性。

8. 发明申请

WO2006071945A2 TECHNIQUES TO MANAGE POWER FOR A MOBILE DEVICE 审中-公开
标题翻译：为移动设备管理电源的技术
公开(公告)号：WO2006071945A2
公开(公告)日：2006-07-06
申请号：PCT/US2005047277
申请日：2005-12-28
申请人： INTEL CORP , ROTEM EFRAIM , BERKOVITZ ARIEL , MENDELSON AVI , NAVEH ALON
发明人： ROTEM EFRAIM , BERKOVITZ ARIEL , MENDELSON AVI , NAVEH ALON
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： System, apparatus, method and article to manage power for a mobile device are described. The apparatus may include a power management module to save an operating context for a processor to at least one memory unit, and reduce power to the processor below a context retention point. Other embodiments are described and claimed.
摘要翻译：描述了用于管理移动设备的功率的系统，设备，方法和文章。该装置可以包括电源管理模块，用于将处理器的操作上下文保存到至少一个存储器单元，并且在上下文保持点下方降低处理器的功率。描述和要求保护其他实施例。

9. 发明专利

JP2011134340A Device, system and method of generating execution instruction based on memory-access instruction 有权
标题翻译：基于存储器访问指令生成执行指令的设备，系统和方法
公开(公告)号：JP2011134340A
公开(公告)日：2011-07-07
申请号：JP2011024488
申请日：2011-02-08
申请人： Intel Corp , インテルコーポレイション
发明人： NAVEH ALON , WEISSMANN ELIEZER , KAZACHINSKY ITAMAR , SORANI IRIS , KAZARINOV YAIR
IPC分类号： G06F9/318 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3234 , G06F1/325 , G06F9/30083
摘要： PROBLEM TO BE SOLVED: To provide a device, system and method for generating execution instruction.
SOLUTION: Embodiments of the present invention provide a device, system, and method for generating an execution instruction. Some demonstrative embodiments include steps of generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed. Some demonstrative embodiments include the device, system and/or method for generating the execution instruction of the predetermined executable format based on the address data of the received memory access instruction. In some demonstrative embodiments, the memory address instruction may be partially converted into the execution instruction.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供用于生成执行指令的装置，系统和方法。解决方案：本发明的实施例提供了一种用于生成执行指令的装置，系统和方法。一些说明性实施例包括基于表示存储器地址的存储器访问指令的存储器地址数据来生成预定可执行格式的执行指令的步骤。描述和要求保护其他实施例。一些说明性实施例包括用于基于接收到的存储器访问指令的地址数据生成预定可执行格式的执行指令的设备，系统和/或方法。在一些演示实施例中，存储器地址指令可以被部分地转换成执行指令。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2007026436A Device, method and system 有权
标题翻译：装置，方法和系统
公开(公告)号：JP2007026436A
公开(公告)日：2007-02-01
申请号：JP2006180086
申请日：2006-06-29
申请人： Intel Corp , インテルコーポレイション
发明人： NAVEH ALON , WEISSMANN ELIEZER , KAZACHINSKY ITAMAR , SORANI IRIS , KAZARINOV YAIR
IPC分类号： G06F9/45 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3234 , G06F1/325 , G06F9/30083
摘要： PROBLEM TO BE SOLVED: To provide an instruction generator which generates an execution instruction of a prescribed executable format based on memory address data of memory-access instruction indicating a memory address. SOLUTION: The present invention provides an apparatus, system and/or method of generating an execution instruction of the prescribed executable format based on the address data of the received memory access instruction. In some demonstrative embodiments of the present invention, the memory address instruction may be converted into the execution instruction at least in part. COPYRIGHT: (C)2007,JPO&INPIT

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