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    • 2. 发明申请
    • NONVOLATILE MEMORY DEVICE
    • 非易失性存储器件
    • US20170011799A1
    • 2017-01-12
    • US14996249
    • 2016-01-15
    • JI-SANG LEEDONGHUN KWAKDAESEOK BYEONCHIWEON YOON
    • JI-SANG LEEDONGHUN KWAKDAESEOK BYEONCHIWEON YOON
    • G11C16/10G11C16/24G11C16/04G11C16/30G11C16/08G11C16/26
    • G11C16/10G11C11/5628G11C11/5642G11C16/0483G11C16/24G11C16/26
    • A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.
    • 非易失性存储器包括存储单元阵列,行解码器电路和页缓冲电路。 行解码器电路响应于从外部设备接收到的写入命令,在第一预充电操作时,对连接到所选存储块的串选择晶体管的串选择线施加导通电压。 页缓冲器电路响应于写入命令,在第一预充电操作下,连接到串选择晶体管的第一电压至位线,而不管加载数据如何,并施加第一电压和 基于所加载的数据,在第二预充电操作中通过第二预充电电路对位线施加第二电压。 在第一预充电操作期间,写数据被加载到页缓冲电路。