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1. 发明申请

US20060103023A1 Methods for incorporating high k dielectric materials for enhanced SRAM operation and structures produced thereby 审中-公开
标题翻译：用于结合高k电介质材料以增强SRAM操作的方法和由此产生的结构
公开(公告)号：US20060103023A1
公开(公告)日：2006-05-18
申请号：US10988484
申请日：2004-11-12
申请人： Azeez Bhavnagarwala , Stephen Kosonocky , Satyanarayana Nitta , Sampath Purushothaman
发明人： Azeez Bhavnagarwala , Stephen Kosonocky , Satyanarayana Nitta , Sampath Purushothaman
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76801 , G11C11/412 , H01L23/53295 , H01L27/11 , H01L27/1104 , H01L2924/0002 , H01L2924/00
摘要： A hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip is described. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.
摘要翻译：描述了在一组区域中具有比在同一微电子芯片上的其它区域更高的互连电容的混合互连结构。提供了几种制造这种结构的方法。描述了这样的混合互连结构的电路实现，其能够增加静态噪声容限并且减少SRAM单元中的泄漏以及用于这种芯片中的SRAM和逻辑的公共电源电压。还教导了能够将这些电路优点与更高的互连性能速度和优异的机械鲁棒性相结合的方法。

2. 发明申请

US20050106762A1 Recovery of hydrophobicity of low-k and ultra low-k organosilicate films used as inter metal dielectrics 失效
标题翻译：用作金属间电介质的低k和超低k有机硅酸盐膜的疏水性的恢复
公开(公告)号：US20050106762A1
公开(公告)日：2005-05-19
申请号：US10853771
申请日：2004-05-25
申请人： Nirupama Chakrapani , Matthew Colburn , Christos Dimitrakopoulos , Dirk Pfeiffer , Sampath Purushothaman , Satyanarayana Nitta
发明人： Nirupama Chakrapani , Matthew Colburn , Christos Dimitrakopoulos , Dirk Pfeiffer , Sampath Purushothaman , Satyanarayana Nitta
IPC分类号： H01L21/00 , H01L21/3105 , H01L21/312 , H01L21/768
CPC分类号： H01L21/76826 , H01L21/02126 , H01L21/02203 , H01L21/31058 , H01L21/76807 , H01L21/76814 , H01L2924/0002 , H01L2924/00
摘要： Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the network. Si—R bonds rarely survive an exposure to plasmas or chemical treatments commonly used in processing; this is especially the case in materials with an open cell pore structure. When Si—R bonds are broken, the materials lose hydrophobicity, due to formation of hydrophilic silanols and low dielectric constant is compromised. A method by which the hydrophobicity of the materials is recovered using a novel class of silylation agents which may have the general formula (R2N)XSiR′Y where X and Y are integers from 1 to 3 and 3 to 1 respectively, and where R and R′ are selected from the group of hydrogen, alkyl, aryl, allyl and a vinyl moiety. Mechanical strength of porous organosilicates is also improved as a result of the silylation treatment.
摘要翻译：通常用于减少集成电路中的RC延迟的是多孔有机硅酸盐的介电膜，其具有二氧化硅像主链与烷基或芳基（以增加材料的疏水性并产生自由体积）直接连接到网络中的Si原子。 Si-R键在暴露于等离子体或通常用于加工的化学处理中很少存活; 这在具有开孔细孔结构的材料中尤其如此。当Si-R键断裂时，材料由于形成亲水硅烷醇而损失疏水性，并且低介电常数受损。使用新型甲硅烷基化剂回收材料的疏水性的方法，其可以具有通式（R 2 N 2）X SiR'Y 其中X和Y分别为1至3和3至1的整数，并且其中R和R'选自氢，烷基，芳基，烯丙基和乙烯基部分。由于甲硅烷基化处理，多孔有机硅酸盐的机械强度也得到改善。

3. 发明申请

US20060264036A1 Line level air gaps 审中-公开
标题翻译：线路气隙
公开(公告)号：US20060264036A1
公开(公告)日：2006-11-23
申请号：US11491816
申请日：2006-07-24
申请人： Shyng-Tsong Chen , Stefanie Chiras , Matthew Colburn , Tomothy Dalton , Jeffrey Hedrick , Elbert Huang , Kaushik Kumar , Michael Lane , Kelly Malone , Chandrasekhar Narayan , Satyanarayana Nitta , Sampath Purushothaman , Robert Rosenberg , Christy Tyberg , Roy Yu
发明人： Shyng-Tsong Chen , Stefanie Chiras , Matthew Colburn , Tomothy Dalton , Jeffrey Hedrick , Elbert Huang , Kaushik Kumar , Michael Lane , Kelly Malone , Chandrasekhar Narayan , Satyanarayana Nitta , Sampath Purushothaman , Robert Rosenberg , Christy Tyberg , Roy Yu
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.
摘要翻译：在多电平微电子集成电路中，空气包括永久线路电介质，超低K材料通过电介质。在通过清洁热分解除去牺牲材料并通过IC结构中的孔隙率辅助副产物扩散后，将空气供应到线路电平。任选地，空气也包括在通孔级电介质中的孔隙中。通过将空气结合到本发明产生的程度，使层内和层间介电值最小化。

4. 发明申请

US20050272341A1 Method for fabricating a self-aligned nanocolumnar airbridge and structure produced thereby 失效
标题翻译：制造自对准纳米柱状空中桥梁的方法及由此制造的结构
公开(公告)号：US20050272341A1
公开(公告)日：2005-12-08
申请号：US11150059
申请日：2005-06-10
申请人： Matthew Colburn , Satyanarayana Nitta , Sampath Purushothaman
发明人： Matthew Colburn , Satyanarayana Nitta , Sampath Purushothaman
IPC分类号： H01J9/14 , H01L21/3205 , H01L21/4763 , H01L21/768 , H01L21/8242 , H01L23/48 , H01L23/52 , H01L23/522 , H01L23/532 , H01L29/06 , H01L29/40
CPC分类号： H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a low k, ultra-low k, and extreme-low k multilayer interconnect structure on a substrate in which the interconnect line features are separated laterally by a dielectric with vertically oriented nano-scale voids formed by perforating it using sub-optical lithography patterning and etching techniques and closing off the tops of the perforations by a dielectric deposition step. The lines are supported either by solid or patterned dielectric features underneath. The method avoids the issues associated with the formation of air gaps after the fabrication of conductor patterns and those associated with the integration of conventional low k, ultra-low k and extreme low k dielectrics which have porosity present before the formation of the interconnect patterns.
摘要翻译：一种用于在衬底上制造低k，超低k和极低k多层互连结构的方法，其中互连线特征由具有垂直取向的纳米级空隙的电介质侧向分开，光刻图案和蚀刻技术，并通过介电沉积步骤封闭穿孔的顶部。线路由固体或图案化的电介质特征支撑。该方法避免了在形成导体图案之后与形成气隙相关的问题，以及与形成互连图案之前具有孔隙率的常规低k，超低k和极低k电介质的集成相关联的问题。

5. 发明申请

US20060258159A1 Process for preparing electronics structures using a sacrificial multilayer hardmask scheme 有权
标题翻译：使用牺牲多层硬掩模方案制备电子结构的方法
公开(公告)号：US20060258159A1
公开(公告)日：2006-11-16
申请号：US11130078
申请日：2005-05-16
申请人： Matthew Colburn , Ricardo Donaton , Conal Murray , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Theodorus Eduardus Fransiscus Standaert , Xiao Liu
发明人： Matthew Colburn , Ricardo Donaton , Conal Murray , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Theodorus Eduardus Fransiscus Standaert , Xiao Liu
IPC分类号： H01B13/00 , H01L21/302 , B44C1/22
CPC分类号： H01L21/32139 , H01L21/0271 , H01L21/31144 , H01L21/7682
摘要： A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.
摘要翻译：用于制备电子结构的方法包括用牺牲多层硬掩模堆叠涂覆衬底叠层，在涂覆在多层硬掩模堆叠的最上层上的抗蚀剂层中形成图案，将图案转移到硬掩模堆叠中，阻挡部分图案，然后将图案的未封闭部分转印到基底叠层中。使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。要强调的是，该摘要被提供以符合要求抽象的规则，这将允许搜索者或其他读者快速地确定技术公开的主题。提交它的理解是，它不会用于解释或限制所附权利要求的范围或含义。

6. 发明申请

US20050233597A1 Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same 审中-公开
标题翻译：用于制备自对准掩模的非光刻方法，由相同制备的制品和用于其的组合物
公开(公告)号：US20050233597A1
公开(公告)日：2005-10-20
申请号：US11143793
申请日：2005-06-02
申请人： Matthew Colburn , Stephen Gates , Jeffrey Hedrick , Elbert Huang , Satyanarayana Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
发明人： Matthew Colburn , Stephen Gates , Jeffrey Hedrick , Elbert Huang , Satyanarayana Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
IPC分类号： H01L21/027 , B32B3/00 , G03F7/00 , G03F7/16 , G03F7/26 , H01L21/31 , H01L21/3105 , H01L21/469
CPC分类号： H05K3/0079 , H01L21/0331 , H01L21/76849 , H05K3/282 , H05K2203/1173 , Y10T428/24802
摘要： A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method.
摘要翻译：一种用于在衬底上的现有图案上形成自对准图案的方法，包括在载体中涂覆含有掩蔽材料的溶液的涂层，所述掩模材料对现有图案的部分具有亲和力; 并且允许掩模材料的至少一部分优先组装到现有图案的部分。该图案可以由具有第一原子组成的衬底的第一组区域和第二组衬底的区域组成，其具有不同于第一组成的第二原子组成。第一组区域可以包括一个或多个金属元件，并且第二组区域可以包括电介质。可以将第一和第二区域处理成具有不同的表面性质。按照该方法制造的结构。用于练习该方法的组合物。

7. 发明申请

US20070138640A1 RECOVERY OF HYDROPHOBICITY OF LOW-K AND ULTRA LOW-K ORGANOSILICATE FILMS USED AS INTER METAL DIELECTRICS 失效
标题翻译：作为金属电介质的低K和超低K有机硅膜的疏水性恢复
公开(公告)号：US20070138640A1
公开(公告)日：2007-06-21
申请号：US11676447
申请日：2007-02-19
申请人： Nirupama Chakrapani , Matthew Colburn , Christops Dimitrakopculos , Dirk Pfeiffer , Sampath Purushothaman , Satyanarayana Nitta
发明人： Nirupama Chakrapani , Matthew Colburn , Christops Dimitrakopculos , Dirk Pfeiffer , Sampath Purushothaman , Satyanarayana Nitta
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L21/76826 , H01L21/02126 , H01L21/02203 , H01L21/31058 , H01L21/76807 , H01L21/76814 , H01L2924/0002 , H01L2924/00
摘要： Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the network. Si—R bonds rarely survive an exposure to plasmas or chemical treatments commonly used in processing; this is especially the case in materials with an open cell pore structure. When Si—R bonds are broken, the materials lose hydrophobicity, due to formation of hydrophilic silanols and low dielectric constant is compromised. A method by which the hydrophobicity of the materials is recovered using a novel class of silylation agents which may have the general formula (R2N)XSiR′Y where X and Y are integers from 1 to 3 and 3 to 1 respectively, and where R and R′ are selected from the group of hydrogen, alkyl, aryl, allyl and a vinyl moiety. Mechanical strength of porous organosilicates is also improved as a result of the silylation treatment.
摘要翻译：通常用于减少集成电路中的RC延迟的是多孔有机硅酸盐的介电膜，其具有二氧化硅像主链与烷基或芳基（以增加材料的疏水性并产生自由体积）直接附着在网络中的Si原子。 Si-R键在暴露于等离子体或通常用于加工的化学处理中很少存活; 这在具有开孔细孔结构的材料中尤其如此。当Si-R键断裂时，材料由于形成亲水硅烷醇而损失疏水性，并且低介电常数受损。使用新型甲硅烷基化剂回收材料的疏水性的方法，其可以具有通式（R 2 N 2）X SiR'Y 其中X和Y分别为1至3和3至1的整数，并且其中R和R'选自氢，烷基，芳基，烯丙基和乙烯基部分。由于甲硅烷基化处理，多孔有机硅酸盐的机械强度也得到改善。

8. 发明申请

US20050208752A1 METHOD FOR FABRICATING A SELF-ALIGNED NANOCOLUMNAR AIRBRIDGE AND STRUCTURE PRODUCED THEREBY 有权
标题翻译：制备自对准纳米核弹体的方法及其生产的结构
公开(公告)号：US20050208752A1
公开(公告)日：2005-09-22
申请号：US10804553
申请日：2004-03-19
申请人： Matthew Colburn , Satyanarayana Nitta , Sampath Purushothaman
发明人： Matthew Colburn , Satyanarayana Nitta , Sampath Purushothaman
IPC分类号： H01J9/14 , H01L21/3205 , H01L21/4763 , H01L21/768 , H01L21/8242 , H01L23/48 , H01L23/52 , H01L23/522 , H01L23/532 , H01L29/06 , H01L29/40
CPC分类号： H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a low k, ultra-low k, and extreme-low k multilayer interconnect structure on a substrate in which the interconnect line features are separated laterally by a dielectric with vertically oriented nano-scale voids formed by perforating it using sub-optical lithography patterning and etching techniques and closing off the tops of the perforations by a dielectric deposition step. The lines are supported either by solid or patterned dielectric features underneath. The method avoids the issues associated with the formation of air gaps after the fabrication of conductor patterns and those associated with the integration of conventional low k, ultra-low k and extreme low k dielectrics which have porosity present before the formation of the interconnect patterns.
摘要翻译：一种用于在衬底上制造低k，超低k和极低k多层互连结构的方法，其中互连线特征由具有垂直取向的纳米级空隙的电介质侧向分开，光刻图案和蚀刻技术，并通过介电沉积步骤封闭穿孔的顶部。线路由固体或图案化的电介质特征支撑。该方法避免了在形成导体图案之后与形成气隙相关的问题，以及与形成互连图案之前具有孔隙率的常规低k，超低k和极低k电介质的集成相关联的问题。

9. 发明申请

US20050208430A1 Method of producing self-aligned mask in conjuction with blocking mask, articles produced by same and composition for same 失效
标题翻译：与阻挡面膜相结合制成自对准面膜的方法，由相同制成的制品和组合物制成
公开(公告)号：US20050208430A1
公开(公告)日：2005-09-22
申请号：US10804552
申请日：2004-03-19
申请人： Matthew Colburn , Satyanarayana Nitta , Sampath Purushothaman
发明人： Matthew Colburn , Satyanarayana Nitta , Sampath Purushothaman
IPC分类号： G03F7/00 , G03F7/20
CPC分类号： G03F7/2022
摘要： A method of forming a self aligned pattern on an existing pattern on a substrate including applying a coating of a solution containing a masking material in a carrier, the masking material being either photo or thermally sensitive; performing a blanket exposure of the substrate; and allowing at least a portion of the masking material to preferentially develop in a fashion that replicates the existing pattern of the substrate. The existing pattern includes a first set of regions of the substrate having a first reflectivity and a second set of regions of the substrate having a second reflectivity different from the first composition. The first set of regions can include one or more metal elements and the second set of regions can include one or more dielectrics. Structures made in accordance with the method. A low resolution mask is used to block out regions over the substrate. Additionally, the resist can be applied over another masking layer that contains a separate pattern.
摘要翻译：一种在衬底上的现有图案上形成自对准图案的方法，包括在载体中涂覆含有掩模材料的溶液的涂层，所述掩模材料为光敏或热敏感的; 进行基板的覆盖曝光; 并且允许至少一部分掩模材料以复制衬底的现有图案的方式优先显影。现有图案包括具有第一反射率的衬底的第一组区域和具有不同于第一组成的第二反射率的衬底的第二组区域。第一组区域可以包括一个或多个金属元素，第二组区域可以包括一个或多个电介质。按照该方法制造的结构。低分辨率掩模用于阻挡衬底上的区域。另外，抗蚀剂可以施加在包含单独图案的另一掩蔽层上。

10. 发明申请

US20050167838A1 DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于减少半导体器件中有效介电常数的器件和方法
公开(公告)号：US20050167838A1
公开(公告)日：2005-08-04
申请号：US10707996
申请日：2004-01-30
申请人： Daniel Edelstein , Matthew Colburn , Edward Cooney , Timothy Dalton , John Fitzsimmons , Jeffrey Gambino , Elbert Huang , Michael Lane , Vincent McGahay , Lee Nicholson , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas Shaw , Andrew Simon , Anthony Stamper
发明人： Daniel Edelstein , Matthew Colburn , Edward Cooney , Timothy Dalton , John Fitzsimmons , Jeffrey Gambino , Elbert Huang , Michael Lane , Vincent McGahay , Lee Nicholson , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas Shaw , Andrew Simon , Anthony Stamper
IPC分类号： H01L21/033 , H01L21/302 , H01L21/311 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/522 , H01L23/532 , H01L29/40
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias
摘要翻译：一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。还可以使用超光刻阻挡掩模。另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。可能禁止在划线车道和通道上或附近形成间隙

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