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1. 发明授权

US06252292B1 Vertical electrical cavity-fuse 失效
标题翻译：垂直电腔保险丝
公开(公告)号：US06252292B1
公开(公告)日：2001-06-26
申请号：US09328960
申请日：1999-06-09
申请人： Axel C. Brintzinger , Roy Iggulden , Stefan J. Weber , Peter Weigand
发明人： Axel C. Brintzinger , Roy Iggulden , Stefan J. Weber , Peter Weigand
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A vertically arranged fuse structure for a semiconductor device. A fuse stud is vertically arranged with respect to a major plane of the semiconductor device and adjacent and electrically connected to overlying electrically conducting material and underlying electrically conducting material. A fuse void is present in the vertically arranged fuse stud. In an unblown state, the fuse provides electrical connection between the overlying electrically conducting material and the underlying electrically conducting material. The electrical connection being breakable by passing electrical energy of a predetermined level through the fuse.
摘要翻译：一种用于半导体器件的垂直布置的熔丝结构。保险丝柱相对于半导体器件的主平面垂直布置，并且相邻并电连接到覆盖的导电材料和下面的导电材料。在垂直布置的保险丝钉中存在保险丝空隙。在未吹塑状态下，保险丝在上覆的导电材料和下面的导电材料之间提供电连接。通过使预定电平的电能通过保险丝而能够使电连接断开。

2. 发明授权

US6136709A Metal line deposition process 有权
标题翻译：金属线沉积工艺
公开(公告)号：US6136709A
公开(公告)日：2000-10-24
申请号：US413265
申请日：1999-10-06
申请人： Sven Schmidbauer , Stefan J. Weber , Peter Weigand , Larry Clevenger , Roy Iggulden
发明人： Sven Schmidbauer , Stefan J. Weber , Peter Weigand , Larry Clevenger , Roy Iggulden
IPC分类号： H01L21/768 , H01L21/24 , H01L21/4763
CPC分类号： H01L21/76877
摘要： A method for depositing metal lines for semiconductor devices, in accordance with the present invention includes the steps of providing a semiconductor wafer including a dielectric layer formed on the wafer, the dielectric layer having vias formed therein and placing the wafer in a deposition chamber. The method further includes depositing a metal on the wafer to fill the vias wherein the metal depositing is initiated when the wafer is at a first temperature and the depositing is continued while heating the wafer to a target temperature which is greater than the first temperature.
摘要翻译：根据本发明的用于沉积半导体器件的金属线的方法包括以下步骤：提供包括在晶片上形成的电介质层的半导体晶片，所述电介质层具有形成在其中的通孔并将晶片放置在沉积室中。该方法还包括在晶片上沉积金属以填充通孔，其中当晶片处于第一温度时开始金属沉积，并且在将晶片加热到大于第一温度的目标温度的同时继续沉积。

3. 发明授权

US06218279B1 Vertical fuse and method of fabrication 有权
公开(公告)号：US06218279B1
公开(公告)日：2001-04-17
申请号：US09512648
申请日：2000-02-24
申请人： Stefan J. Weber , Axel Christoph Brintzinger , Roy Iggulden , Mark Hoinkis , Chandrasekhar Narayan , Robert Van den Berg
发明人： Stefan J. Weber , Axel Christoph Brintzinger , Roy Iggulden , Mark Hoinkis , Chandrasekhar Narayan , Robert Van den Berg
IPC分类号： H01L2144
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.

4. 发明授权

US06242789B1 Vertical fuse and method of fabrication 失效
标题翻译：垂直保险丝和制造方法
公开(公告)号：US06242789B1
公开(公告)日：2001-06-05
申请号：US09255767
申请日：1999-02-23
申请人： Stefan J. Weber , Axel Christoph Brintzinger , Roy Iggulden , Mark Hoinkis , Chandrasekhar Narayan , Robert Van Den Berg
发明人： Stefan J. Weber , Axel Christoph Brintzinger , Roy Iggulden , Mark Hoinkis , Chandrasekhar Narayan , Robert Van Den Berg
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.
摘要翻译：根据本发明的用于半导体器件的熔丝包括：具有设置在其表面上的导电通路的基板，设置在基板上的电介质层和垂直于通过介电层垂直于表面设置并连接到导电路径的熔丝垂直熔丝形成具有沿着空腔的垂直表面设置的衬垫材料的空腔，垂直表面被熔化以熔断熔断器。还包括制造垂直保险丝的方法。

5. 发明授权

US6057236A CVD/PVD method of filling structures using discontinuous CVD AL liner 失效
标题翻译：使用不连续CVD AL衬垫填充结构的CVD / PVD方法
公开(公告)号：US6057236A
公开(公告)日：2000-05-02
申请号：US105644
申请日：1998-06-26
申请人： Larry Clevenger , Mark Hoinkis , Roy C. Iggulden , Stefan J. Weber
发明人： Larry Clevenger , Mark Hoinkis , Roy C. Iggulden , Stefan J. Weber
IPC分类号： H01L21/3205 , C23C14/14 , C23C14/58 , C23C16/56 , C23C28/02 , H01L21/28 , H01L21/768 , H01L23/52 , H01L23/522 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/76868 , H01L21/76876 , H01L21/76882 , H01L23/5226 , H01L2924/0002
摘要： Improved methods for forming metal-filled structures in openings on substrates for integrated circuit devices are obtained by the formation of a discontinuous metal liner by CVD in an opening to be filled. The discontinuous metal liner surprisingly provides wetting equivalent to or better than continuous layer CVD liners. The CVD step is followed by depositing a further amount of metal by physical vapor deposition over the discontinuous layer in the opening, and reflowing the further amount of metal to obtain the metal-filled structure.The interior surface of the opening is preferably a conductive material such as titanium nitride. Preferably, the discontinuous metal layer is made of aluminum. The metal deposited by PVD is preferably aluminum or an aluminum alloy. The methods of the invention are especially useful for the filling of contact holes, damascene trenches and dual damascene trenches. The methods of the invention are especially useful for filling structures having an opening width less than 250 nm.
摘要翻译：通过在待填充的开口中通过CVD形成不连续的金属衬垫来获得用于在集成电路器件的衬底上的开口中形成金属填充结构的改进方法。不连续的金属衬垫令人惊讶地提供了与连续层CVD衬垫相当或更好的润湿。 CVD步骤之后，通过在开口中的不连续层上的物理气相沉积沉积更多量的金属，再回流另外的金属以获得填充金属的结构。开口的内表面优选为诸如氮化钛的导电材料。优选地，不连续金属层由铝制成。通过PVD沉积的金属优选为铝或铝合金。本发明的方法对于填充接触孔，镶嵌沟槽和双镶嵌沟槽特别有用。本发明的方法对于填充具有小于250nm的开口宽度的结构特别有用。

6. 发明授权

US06261937B1 Method for forming a semiconductor fuse 失效
标题翻译：形成半导体保险丝的方法
公开(公告)号：US06261937B1
公开(公告)日：2001-07-17
申请号：US09105107
申请日：1998-06-24
申请人： Dirk Többen , Stefan J. Weber , Axel Brintzinger
发明人： Dirk Többen , Stefan J. Weber , Axel Brintzinger
IPC分类号： H01L2144
CPC分类号： H01L21/76888 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a semiconductor integrated circuit having a fuse and an active device. A dielectric layer is formed over the fuse and over a contract region of the active device. Via holes are formed through selected regions of the dielectric layer exposing underlying portions of the fuse and underlying portions of a contact region of the active device. An electrically conductive material is deposited over the dielectric layer and through the via holes onto exposed portions of the fuse and the contact region. Portions of the electrically conductive material deposited onto the fuse are selectively removed while leaving portions of the electrically conductive material deposited onto the contact region of the active device. A fill material is disposed in the one of the fuse, a bottom portion of such filling material being spaced from the fuse.
摘要翻译：一种用于形成具有熔丝和有源器件的半导体集成电路的方法。在保险丝上方并在有源器件的合约区域上形成介电层。通过介电层的选定区域形成通孔，该电介质层暴露熔丝的下面部分和有源器件的接触区域的下面部分。将导电材料沉积在电介质层上并通过通孔到保险丝和接触区域的暴露部分上。选择性地去除沉积在熔丝上的导电材料的部分，同时留下部分导电材料沉积在有源器件的接触区域上。一个填充材料设置在保险丝中的一个中，这种填充材料的底部与保险丝间隔开。

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