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1. 发明授权

US06228277B1 Etch endpoint detection 有权
标题翻译：蚀刻端点检测
公开(公告)号：US06228277B1
公开(公告)日：2001-05-08
申请号：US09172456
申请日：1998-10-14
申请人： Avinoam Kornblit , Tseng-Chung Lee , Heon Lee , Helen Louise Maynard
发明人： Avinoam Kornblit , Tseng-Chung Lee , Heon Lee , Helen Louise Maynard
IPC分类号： H01L2166
CPC分类号： H01L22/26 , G01B11/0683 , H01J37/32935 , H01J2237/334
摘要： The specification describes an interferometric in-situ end point detection technique for plasma etching in which the end point is predicted before any overetching occurs. It is based on the recognition that the wavelength of the monitoring beam can be selected so that only a single interferometric fringe appears before clearing. Knowing there is only one fringe, detection is simplified and the etching process can be terminated while a finite but small thickness of the layer remains. This allows etching partial thicknesses of layers. It also allows a two step etch process wherein the etch chemistry can be changed to a highly selective etch to complete clearing of the layer.
摘要翻译：本说明书描述了用于等离子体蚀刻的干涉式原位终点检测技术，其中在任何过蚀刻发生之前预测终点。基于这样的认识，可以选择监测光束的波长，使得在清除之前仅出现单个干涉条纹。知道只有一个边缘，检测被简化，并且蚀刻过程可以终止，同时层的有限但较小的厚度保留。这允许蚀刻层的部分厚度。它还允许两步蚀刻工艺，其中蚀刻化学物质可以改变为高选择性蚀刻以完成层的清除。

2. 发明授权

US5653894A Active neural network determination of endpoint in a plasma etch process 失效
标题翻译：等离子体蚀刻工艺中的端点的主动神经网络测定
公开(公告)号：US5653894A
公开(公告)日：1997-08-05
申请号：US446122
申请日：1995-05-19
申请人： Dale Edward Ibbotson , Tseng-Chung Lee , Helen Louise Maynard , Edward Alois Rietman
发明人： Dale Edward Ibbotson , Tseng-Chung Lee , Helen Louise Maynard , Edward Alois Rietman
IPC分类号： G06F15/18 , G05B13/02 , G06N3/00 , H01J37/32 , H01L21/302 , H01L21/3065 , G01N21/00 , H05H1/00
CPC分类号： H01J37/32935 , G05B13/027 , H01J37/32963
摘要： The present invention is predicated upon the fact that a process signature from a plasma process used in fabricating integrated circuits contains information about phenomena which cause variations in the fabrication process such as age of the plasma reactor, densities of the wafers exposed to the plasma, chemistry of the plasma, and concentration of the remaining material. In accordance with the present invention, a method for using neural networks to determine plasma etch end-point times in an integrated circuit fabrication process is disclosed. The end-point time is based on in-situ monitoring of at least two parameters during the plasma etch process. After the neural network is trained to associate a certain condition or set of conditions with the endpoint of the process, the neural network is used to control the process.
摘要翻译：本发明基于以下事实：来自用于制造集成电路的等离子体工艺的工艺特征包含关于引起制造工艺变化的现象的信息，例如等离子体反应器的年龄，暴露于等离子体的晶片的密度，化学的等离子体和剩余材料的浓度。根据本发明，公开了一种使用神经网络来确定集成电路制造工艺中的等离子体蚀刻终点时间的方法。终点时间基于在等离子体蚀刻过程期间至少两个参数的原位监测。在训练神经网络以将某一条件或一组条件与过程的端点相关联之后，使用神经网络来控制该过程。

3. 发明授权

US06750495B1 Damascene capacitors for integrated circuits 有权
标题翻译：用于集成电路的大马士革电容器
公开(公告)号：US06750495B1
公开(公告)日：2004-06-15
申请号：US09310388
申请日：1999-05-12
申请人： Glenn B. Alers , Tseng-Chung Lee , Helen Louise Maynard , Daniel Joseph Vitkavage
发明人： Glenn B. Alers , Tseng-Chung Lee , Helen Louise Maynard , Daniel Joseph Vitkavage
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , H01L27/10852 , H01L28/55 , H01L28/91
摘要： A capacitor structure is formed in a window in a dielectric layer of an integrated circuit. The lower electrode (or plate) is disposed on a portion side surface of the cavity but not on the top surface of the dielectric. A layer of dielectric material is disposed on the lower electrode and upon the top surface of the integrated circuit dielectric. Finally, an upper electrode (or plate) is disposed on the layer of dielectric material. Because the lower electrode is removed from a portion of the cavity sidewall and top surface of the dielectric shorting problems which could result during planarization are avoided. A technique for fabricating an integrated circuit (IC) for use in multi-level structures is also disclosed. The technique is readily incorporated into standard multi-level processing techniques. After a window is opened in the particular dielectric layer of the IC, a conductive layer is deposited in the window and forms the lower plate of a capacitor. The lower plate is then etched so that it is removed from a portion of the sidewalls and from the top surface of the dielectric layer. After the lower electrode is etched, a dielectric material is disposed in the cavity and on the top surface of the dielectric layer. A second layer of conductor is disposed on top of the dielectric material layer, thus completing the capacitor structure.
摘要翻译：在集成电路的电介质层的窗口中形成电容器结构。下电极（或板）设置在空腔的部分侧表面上，但不设置在电介质的顶表面上。介电材料层设置在下电极上和集成电路电介质的顶表面上。最后，在电介质材料层上设置上电极（或板）。因为下部电极从空腔侧壁的一部分移除，并且避免了在平坦化期间可能导致的电介质短路问题的顶表面。还公开了一种用于制造用于多层结构的集成电路（IC）的技术。该技术很容易并入标准的多级处理技术。在IC的特定电介质层中打开窗口之后，在窗口中沉积导电层并形成电容器的下板。然后蚀刻下板，使其从侧壁的一部分和从电介质层的顶表面去除。在蚀刻下部电极之后，介电材料设置在空腔中并在电介质层的顶表面上。第二层导体设置在介电材料层的顶部，从而完成电容器结构。

4. 发明授权

US5835221A Process for fabricating a device using polarized light to determine film thickness 失效
标题翻译：使用偏振光制造器件以确定膜厚度的方法
公开(公告)号：US5835221A
公开(公告)日：1998-11-10
申请号：US714909
申请日：1996-09-17
申请人： Tseng-Chung Lee , Helen Louise Maynard
发明人： Tseng-Chung Lee , Helen Louise Maynard
IPC分类号： G01B11/06 , H01L21/302 , H01L21/3065 , H01L21/66 , G01J4/04
CPC分类号： G01B11/0616
摘要： A process for device fabrication in which polarized light is used to monitor film thickness. The polarized light is made incident on the surface of a substrate with a film thereon that has a different reflectivity than that of the underlying substrate. The surface of the film is non-planar, either by virtue of the fact that the film is formed over a substrate with a non-planar surface, or because there is a patterned layer formed over the film, or both. The substrate is subjected to conditions that change the thickness of the film on the substrate. The polarized light that is reflected from the substrate is detected at a selected wavelength or wavelengths and a trace of the intensity of the reflected light both parallel and perpendicular to the substrate surface over time is obtained. This trace is compared to a model trace which is obtained by approximating the film thickness, and the relative amount of the areas of different reflectivity on the substrate surface. The film thickness used to generate the model trace is adjusted to obtain a desired correspondence between the model trace and the actual trace. When the desired correspondence is obtained, then the film thickness used to obtain the model trace with the desired correspondence is the determined film thickness.
摘要翻译：用于器件制造的方法，其中使用偏振光来监测膜厚度。使偏振光入射到其上具有与底层基板的反射率不同的膜的基板的表面上。膜的表面是非平面的，无论是由于在非平面表面的衬底上形成膜，或者由于在膜上形成图案层，或者两者都形成。基板经受改变基板上的膜厚度的条件。以选定的波长或波长检测从基板反射的偏振光，并且获得随时间平行且垂直于基板表面的反射光的强度的迹线。将该迹线与通过近似膜厚度获得的模型轨迹以及衬底表面上不同反射率的面积的相对量进行比较。调整用于产生模型轨迹的膜厚以获得模型轨迹和实际轨迹之间的期望的对应关系。当获得所需的对应关系时，用于获得具有所需对应关系的模型轨迹的膜厚度是确定的膜厚度。

5. 发明授权

US06541149B1 Article comprising micro fuel cell 有权
标题翻译：文章包含微型燃料电池
公开(公告)号：US06541149B1
公开(公告)日：2003-04-01
申请号：US09514494
申请日：2000-02-29
申请人： Helen Louise Maynard , Jeremy Patrick Meyers
发明人： Helen Louise Maynard , Jeremy Patrick Meyers
IPC分类号： H01M486
CPC分类号： H01M8/1007 , H01M8/241 , Y10T156/10
摘要： Improved micro fuel cells suitable for portable electrical devices are provided, and processes for forming such cells. In one embodiment of the invention, silicon substrates are used both as the gas delivery structure for the fuel and the oxidant, and as the current collectors. Such use of silicon is advantageous in that it becomes possible both to utilize micromachining and lithographic techniques to form the desired structures, e.g., the gas delivery channels, and also to integrate the fuel cell with silicon-based control circuitry. Advantageously, the silicon substrates comprise both gas delivery tunnels and porous silicon gas diffusion regions formed over the tunnels in the surface of the substrate, i.e., the porous regions over the gas delivery tunnels are integral with the silicon substrate. In another embodiment of the invention, a monolithic structure is employed. In this structure, in contrast to the sandwich-type structure of the previous embodiment, a single silicon substrate—not acting as a current collector—is used, with all flow systems contained therein.
摘要翻译：提供了适用于便携式电气装置的改进的微型燃料电池，以及用于形成这种电池的工艺。在本发明的一个实施例中，硅衬底既用作燃料和氧化剂的气体输送结构，也用作集电器。硅的这种使用是有利的，因为有可能利用微机械加工和平版印刷技术来形成所需的结构，例如气体输送通道，以及将燃料电池与基于硅的控制电路集成。有利地，硅衬底包括形成在衬底表面上的隧道上方的气体输送隧道和多孔硅气体扩散区域，即气体输送隧道上的多孔区域与硅衬底是一体的。在本发明的另一个实施例中，采用整体结构。在该结构中，与前述实施例的夹层结构相反，使用不用作集电器的单个硅衬底，其中包含所有流动系统。

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