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1. 发明授权

US07562206B2 Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions 有权
标题翻译：用于动态和静态预测指令资源利用率以生成执行集群分区的多级方案
公开(公告)号：US07562206B2
公开(公告)日：2009-07-14
申请号：US11323043
申请日：2005-12-30
申请人： Avinash Sodani , Alexandre J. Farcy , Stephan J. Jourdan , Per Hammarlund , Mark C. Davis
发明人： Avinash Sodani , Alexandre J. Farcy , Stephan J. Jourdan , Per Hammarlund , Mark C. Davis
IPC分类号： G06F9/30
CPC分类号： G06F9/30101 , G06F9/3012 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3885 , G06F9/3891
摘要： Microarchitecture policies and structures to predict execution clusters and facilitate inter-cluster communication are disclosed. In disclosed embodiments, sequentially ordered instructions are decoded into micro-operations. Execution of one set of micro-operations is predicted to involve execution resources to perform memory access operations and inter-cluster communication, but not to perform branching operations. Execution of a second set of micro-operations is predicted to involve execution resources to perform branching operations but not to perform memory access operations. The micro-operations are partitioned for execution in accordance with these predictions, the first set of micro-operations to a first cluster of execution resources and the second set of micro-operations to a second cluster of execution resources. The first and second sets of micro-operations are executed out of sequential order and are retired to represent their sequential instruction ordering.
摘要翻译：公开了用于预测执行群集并促进群集间通信的微架构策略和结构。在所公开的实施例中，顺序排序的指令被解码成微操作。预计执行一组微操作涉及执行资源以执行存储器访问操作和集群间通信，但不执行分支操作。预计第二组微操作的执行涉及执行资源以执行分支操作，但不执行存储器访问操作。根据这些预测将微操作划分为执行，即第一组执行资源的第一组微操作和第二组执行资源的第二组微操作。第一组和第二组微操作按顺序执行，并退出以表示其顺序指令排序。

2. 发明授权

US07475225B2 Method and apparatus for microarchitecture partitioning of execution clusters 有权
标题翻译：执行集群的微架构划分方法和装置
公开(公告)号：US07475225B2
公开(公告)日：2009-01-06
申请号：US11322768
申请日：2005-12-30
申请人： Stephan J. Jourdan , Avinash Sodani , Alexandre J. Farcy , Per Hammarlund , Sebastien Hily , Mark C. Davis
发明人： Stephan J. Jourdan , Avinash Sodani , Alexandre J. Farcy , Per Hammarlund , Sebastien Hily , Mark C. Davis
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30101 , G06F9/3012 , G06F9/3828 , G06F9/3838 , G06F9/384 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3885 , G06F9/3891
摘要： Microarchitecture policies and structures partition execution resource clusters. In disclosed microarchitecture embodiments, micro-operations representing a sequential instruction ordering are partitioned into a two sets. To one set of micro-operations execution resources are allocated from a cluster of execution resources that can perform memory access operations but not branching operations. To the other set of micro-operations execution resources are allocated from a cluster of execution resources that can perform branching operations but not memory access operations. The first and second sets of micro-operations may be executed out of sequential order but are retired to represent their sequential instruction ordering.
摘要翻译：微架构策略和结构分区执行资源集群。在公开的微架构实施例中，表示顺序指令排序的微操作被划分成两组。对于一组微操作执行资源从可执行存储器访问操作而不是分支操作的执行资源集群分配。对另一组微操作执行资源从可执行分支操作而不是存储器访问操作的执行资源集群分配。第一组和第二组微操作可以按顺序执行，但是退休以表示其顺序指令排序。

3. 发明申请

US20140195790A1 PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
标题翻译：具有分支机构错误预测的第二个执行单元的处理程序
公开(公告)号：US20140195790A1
公开(公告)日：2014-07-10
申请号：US13994676
申请日：2011-12-28
申请人： Matthew C. Merten , Avinash Sodani , Sean P. Mirkes , Vijaykumar B. Kadgi , Bambang Sutanto , Chia Yin Kevin Lai , Morris Marden , Alexandre J. Farcy
发明人： Matthew C. Merten , Avinash Sodani , Sean P. Mirkes , Vijaykumar B. Kadgi , Bambang Sutanto , Chia Yin Kevin Lai , Morris Marden , Alexandre J. Farcy
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F9/3885
摘要： A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary JEU is skidded into the primary JEU's dispatch pipeline such that the branch processing for the secondary JEU occurs after processing of the branch for the primary JEU and while the primary JEU is not processing a branch. Moreover, in cases when a nuke command is also received from a reorder buffer of the processor, the branch processing for the secondary JEU is further delayed to accommodate processing of the nuke on the primary JEU. Further embodiments support the promotion of the secondary JEU to have access to the mispredict mechanisms of the primary JEU in certain circumstances.
摘要翻译：次级跳转执行单元（JEU）并入微处理器以与主JEU同时操作，使得能够执行同时分支操作，并可能检测到多个分支错误预测。当在同一个指令周期中对两个JEU执行分支操作时，辅助JEU的错误预测处理被划分到主JEU的调度流水线中，使得辅助JEU的分支处理在主JEU的分支处理之后发生，而初级JEU不处理分支。此外，在从处理器的重新排序缓冲器接收到nuke命令的情况下，进一步延迟用于辅助JEU的分支处理，以适应主JEU上的nuke的处理。进一步的实施方案支持促进联合联合国次级方案在某些情况下获得主要联合执行机构的错误预测机制。

4. 发明授权

US07711898B2 Register alias table cache to map a logical register to a physical register 有权
标题翻译：注册别名表缓存将逻辑寄存器映射到物理寄存器
公开(公告)号：US07711898B2
公开(公告)日：2010-05-04
申请号：US10737760
申请日：2003-12-18
申请人： Avinash Sodani , Stephan J. Jourdan , Samie B. Samaan
发明人： Avinash Sodani , Stephan J. Jourdan , Samie B. Samaan
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： Embodiments of the present invention relate to a system and method for implementing functions of a register translation table of a computer processor, with reduced area requirements as compared to known arrangements. In one embodiment, an apparatus may comprise a register alias table cache to map a logical register to a physical register. The register alias table cache may have a capacity corresponding to a subset of architectural logical registers. The apparatus may further comprise store logic coupled to the cache to perform operations to save an existing content of the physical register if a cache entry corresponding to the logical register is evicted from the cache. The apparatus may also comprise load logic coupled to the cache to perform operations to load a content to the physical register and to form a new entry in the cache if a needed mapping is not present in the cache.
摘要翻译：本发明的实施例涉及一种用于实现计算机处理器的寄存器转换表的功能的系统和方法，与已知布置相比，其面积要求减小。在一个实施例中，装置可以包括寄存器别名表高速缓存以将逻辑寄存器映射到物理寄存器。寄存器别名表缓存可以具有对应于体系结构逻辑寄存器子集的容量。如果与逻辑寄存器对应的高速缓存条目从高速缓存中逐出，则该设备还可以包括耦合到高速缓存的存储逻辑，以执行操作以保存物理寄存器的现有内容。该装置还可以包括耦合到高速缓存的负载逻辑，以执行将内容加载到物理寄存器的操作，并且如果高速缓存中不存在必需的映射，则在高速缓存中形成新的条目。

5. 发明授权

US07502912B2 Method and apparatus for rescheduling operations in a processor 失效
标题翻译：用于在处理器中重新调度操作的方法和装置
公开(公告)号：US07502912B2
公开(公告)日：2009-03-10
申请号：US10749272
申请日：2003-12-30
申请人： Avinash Sodani , Per H. Hammarlund , Stephan J. Jourdan
发明人： Avinash Sodani , Per H. Hammarlund , Stephan J. Jourdan
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861
摘要： A method and apparatus for rescheduling operations in a processor. More particularly, the present invention relates to optimally using a scheduler resource in a processor by analyzing, predicting, and sorting the write order of instructions into the scheduler so that the duration the instructions sit idle in the scheduler is minimized. The analyses, prediction, and sorting may be done between an instruction queue and a scheduler by using delay units. The prediction can be based on history (latency, dependency, and resource) or on a general prediction scheme.
摘要翻译：一种用于在处理器中重新调度操作的方法和装置。更具体地说，本发明涉及通过分析，预测和排序指令的写入顺序来最优化地使用处理器中的调度器资源，使得指令在调度器中空闲的持续时间最小化。分析，预测和排序可以通过使用延迟单元在指令队列和调度器之间完成。预测可以基于历史（延迟，依赖和资源）或一般预测方案。

6. 发明授权

US07529913B2 Late allocation of registers 失效
标题翻译：寄存器后期分配
公开(公告)号：US07529913B2
公开(公告)日：2009-05-05
申请号：US10743065
申请日：2003-12-23
申请人： Avinash Sodani , Per H. Hammarlund , Stephan J. Jourdan
发明人： Avinash Sodani , Per H. Hammarlund , Stephan J. Jourdan
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30098 , G06F9/30181 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： Embodiments of the present invention relate to a method and system for providing virtual identifiers corresponding to physical registers in a computer processor. According to the embodiments, the virtual identifiers may be used to represent the physical registers during operations in a pipeline of the processor.
摘要翻译：本发明的实施例涉及一种用于提供与计算机处理器中的物理寄存器相对应的虚拟标识符的方法和系统。根据实施例，虚拟标识符可以用于在处理器的流水线中的操作期间表示物理寄存器。

7. 发明申请

US20050149702A1 Method and system for memory renaming 有权
标题翻译：用于内存重命名的方法和系统
公开(公告)号：US20050149702A1
公开(公告)日：2005-07-07
申请号：US10745700
申请日：2003-12-29
申请人： Sebastien Hily , Per Hammarlund , Avinash Sodani
发明人： Sebastien Hily , Per Hammarlund , Avinash Sodani
IPC分类号： G06F9/00 , G06F9/312 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3842 , G06F9/30043 , G06F9/3017 , G06F9/384 , G06F9/3861
摘要： Embodiments of the present invention provide a method, apparatus and system for memory renaming. In one embodiment, a decode unit may decode a load instruction. If the load instruction is predicted to be memory renamed, the load instruction may have a predicted store identifier associated with the load instruction. The decode unit may transform the load instruction that is predicted to be memory renamed into a data move instruction and a load check instruction. The data move instruction may read data from the cache based on the predicted store identifier and load check instruction may compare an identifier associated with an identified source store with the predicted store identifier. A retirement unit may retire the load instruction if the predicted store identifier matches an identifier associated with the identified source store. In another embodiment of the present invention, the processor may re-execute the load instruction without memory renaming if the predicted store identifier does not match the identifier associated with the identified source store.
摘要翻译：本发明的实施例提供了一种用于存储器重命名的方法，装置和系统。在一个实施例中，解码单元可以解码加载指令。如果加载指令被预测为存储器重新命名，则加载指令可以具有与加载指令相关联的预测存储标识符。解码单元可以将预测为被重命名的存储器的加载指令变换为数据移动指令和加载检查指令。数据移动指令可以基于预测的存储标识符从高速缓存读取数据，并且加载检查指令可以将与所识别的源存储器相关联的标识符与预测的存储标识符进行比较。如果预测的商店标识符与与所标识的源商店相关联的标识符匹配，则退休单元可以退出加载指令。在本发明的另一个实施例中，如果预测的存储标识符与与所识别的源存储器相关联的标识符不匹配，则处理器可以重新执行加载指令而不进行存储器重命名。

8. 发明申请

US20140052963A1 TECHNIQUE TO PERFORM THREE-SOURCE OPERATIONS 有权
标题翻译：执行三源操作的技术
公开(公告)号：US20140052963A1
公开(公告)日：2014-02-20
申请号：US14063789
申请日：2013-10-25
申请人： Avinash Sodani , Stephan Jourdan , Alexandre Farcy , Per Hammarlund
发明人： Avinash Sodani , Stephan Jourdan , Alexandre Farcy , Per Hammarlund
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3017 , G06F9/45504
摘要： A technique to perform three-source instructions. At least one embodiment of the invention relates to converting a three-source instruction into at least two instructions identifying no more than two source values.
摘要翻译：一种执行三源指令的技术。本发明的至少一个实施例涉及将三源指令转换成标识不超过两个源值的至少两个指令。

9. 发明申请

US20070283129A1 Vector length tracking mechanism 审中-公开
标题翻译：矢量长度跟踪机制
公开(公告)号：US20070283129A1
公开(公告)日：2007-12-06
申请号：US11321022
申请日：2005-12-28
申请人： Stephan Jourdan , Avinash Sodani , Michael Fetterman , Per Hammarlund , Glenn Hinton
发明人： Stephan Jourdan , Avinash Sodani , Michael Fetterman , Per Hammarlund , Glenn Hinton
IPC分类号： G06F15/00
CPC分类号： G06F9/3017 , G06F9/30036 , G06F9/30192 , G06F9/3836
摘要： According to one embodiment, a method is disclosed. The method includes receiving a value at a vector length (VL) tracker and establishing a VL for subsequent micro-operations (μops) that are to be executed corresponding to the value.
摘要翻译：根据一个实施例，公开了一种方法。该方法包括：在向量长度（VL）跟踪器处接收一个值，并为对应于该值执行的后续微操作（muops）建立一个VL。

10. 发明申请

US20070143575A1 Flow optimization and prediction for VSSE memory operations 有权
标题翻译： VSSE存储器操作的流优化和预测
公开(公告)号：US20070143575A1
公开(公告)日：2007-06-21
申请号：US11315964
申请日：2005-12-21
申请人： Stephen Jourdan , Per Hammarlund , Michael Fetterman , Michael Cornaby , Glenn Hinton , Avinash Sodani
发明人： Stephen Jourdan , Per Hammarlund , Michael Fetterman , Michael Cornaby , Glenn Hinton , Avinash Sodani
IPC分类号： G06F15/00
CPC分类号： G06F9/345 , G06F9/3017 , G06F9/325 , G06F9/3455 , G06F9/3844
摘要： In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises generating an optimized micro-operation (μop) flow for an instruction to operate on a vector if the instruction is predicted to be unmasked and unit-stride, the instruction to access elements in memory, and accessing via the optimized μop flow two or more of the elements at the same time without determining masks of the two or more elements. Other embodiments are also described.
摘要翻译：在一个实施例中，公开了一种用于向量流单个指令，多数据（SIMD）扩展（VSSE）存储器操作的流优化和预测的方法。该方法包括：如果预测指令是未屏蔽和单步的，则生成用于对矢量进行操作的指令的优化的微操作（muop）流程，访问存储器中的元件的指令以及经由优化的muop流2访问或更多的元素，而不确定两个或更多个元件的掩模。还描述了其它实施例。

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