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1. 发明申请

US20110215852A1 HIGH SPEED LATCH CIRCUIT WITH METASTABILITY TRAP AND FILTER 失效
标题翻译：具有耐腐蚀性和过滤器的高速锁闩电路
公开(公告)号：US20110215852A1
公开(公告)日：2011-09-08
申请号：US13036033
申请日：2011-02-28
申请人： Avi KLEIN , Migel JACUBOVSKI
发明人： Avi KLEIN , Migel JACUBOVSKI
IPC分类号： H03L7/00
CPC分类号： H03L7/00
摘要： A synchronizer constituted of a first and second set of three serially coupled latches coupled to a common clocking signal, the first and the ultimate latch of the first set responsive to a first edge of a common clocking signal and the penultimate latch responsive to an opposing edge of the common clocking signal, the second set being respectively responsive to the respective complementary edges of the clocking signal; an input lead arranged to receive a signal to be synchronized, the input lead coupled to the input of the first latch of the first set and to the input of the first latch of the second set; and a filter arranged to pass the output of each of the first set and the second set responsive to the penultimate latch of the set exhibiting a consistent output for two consecutive opposing edges.
摘要翻译：同步器由耦合到公共时钟信号的第三组串联耦合的锁存器构成，响应于公共时钟信号的第一边缘的第一集合的第一和最终锁存器以及对应的边沿的倒数第二个锁存器所述第二组分别响应所述时钟信号的相应互补边缘; 输入引线，被布置为接收要同步的信号，所述输入引线耦合到所述第一组的第一锁存器的输入端和所述第二组的第一锁存器的输入端; 以及滤波器，其布置成响应于对于两个连续的相对边缘呈现一致的输出的该组的倒数第二个锁定来传递第一组和第二组中的每一个的输出。

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