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1. 发明授权

US07772076B2 Method of manufacturing semiconductor device using dummy gate wiring layer 失效
标题翻译：使用伪栅极布线层制造半导体器件的方法
公开(公告)号：US07772076B2
公开(公告)日：2010-08-10
申请号：US11715965
申请日：2007-03-09
申请人： Atsushi Yagishita , Kouji Matsuo , Yasushi Akasaka , Kyoichi Suguro , Yoshitaka Tsunashima
发明人： Atsushi Yagishita , Kouji Matsuo , Yasushi Akasaka , Kyoichi Suguro , Yoshitaka Tsunashima
IPC分类号： H01L21/336
CPC分类号： H01L29/66575 , H01L21/823418 , H01L21/823437 , H01L21/823475 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823878 , H01L27/11 , H01L27/1104 , H01L29/1033 , H01L29/41775 , H01L29/41783 , H01L29/66545 , H01L29/78 , Y10S438/926
摘要： A method of manufacturing a semiconductor device includes forming a dummy gate wiring layer having a side surface and an upper surface on a first area of one major surface of a substrate, the major surface of the substrate including the first area and a second area, thereafter, forming a semiconductor film on the second area of the major surface of the substrate by using epitaxial growth, the semiconductor film having a thickness smaller than a thickness of the dummy gate wiring layer, and forming, on the semiconductor film, a gate sidewall which is made of an insulator and covers the side surface of the dummy gate wiring layer.
摘要翻译：一种制造半导体器件的方法包括在衬底的一个主表面的第一区域上形成具有侧表面和上表面的虚拟栅极布线层，所述衬底的主表面包括第一区域和第二区域，之后通过使用外延生长在所述衬底的主表面的第二区域上形成半导体膜，所述半导体膜的厚度小于所述虚拟栅极布线层的厚度，并且在所述半导体膜上形成栅极侧壁，所述栅极侧壁由绝缘体制成并覆盖虚拟栅极布线层的侧表面。

2. 发明授权

US07208797B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07208797B2
公开(公告)日：2007-04-24
申请号：US10023849
申请日：2001-12-21
申请人： Atsushi Yagishita , Kouji Matsuo , Yasushi Akasaka , Kyoichi Suguro , Yoshitaka Tsunashima
发明人： Atsushi Yagishita , Kouji Matsuo , Yasushi Akasaka , Kyoichi Suguro , Yoshitaka Tsunashima
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L29/66575 , H01L21/823418 , H01L21/823437 , H01L21/823475 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823878 , H01L27/11 , H01L27/1104 , H01L29/1033 , H01L29/41775 , H01L29/41783 , H01L29/66545 , H01L29/78 , Y10S438/926
摘要： There is provided a semiconductor device including a substrate, a device isolation insulating film formed on the substrate, a gate electrode formed on the substrate, a gate wiring layer formed in the device isolation insulating film and connected to the gate electrode, source and drain electrodes arranged on the substrate to face each other via the gate electrode, and an insulating film covering bottom and side surfaces of each of the gate electrode and the gate wiring layer, wherein the gate, source and drain electrodes and gate wiring layer have upper surface levels equal to or lower than that of the device isolation insulating film.
摘要翻译：提供了一种半导体器件，包括衬底，在衬底上形成的器件隔离绝缘膜，形成在衬底上的栅电极，形成在器件隔离绝缘膜中并连接到栅电极的栅极布线层，源极和漏极布置在基板上，经由栅极电极相对对置;以及绝缘膜，其覆盖栅极电极和栅极布线层中的每一个的底部和侧面，其中栅极，源极和漏极以及栅极布线层具有上表面水平等于或低于器件绝缘膜的绝缘膜。

3. 发明授权

US06346438B1 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06346438B1
公开(公告)日：2002-02-12
申请号：US09105960
申请日：1998-06-29
申请人： Atsushi Yagishita , Kouji Matsuo , Yasushi Akasaka , Kyoichi Suguro , Yoshitaka Tsunashima
发明人： Atsushi Yagishita , Kouji Matsuo , Yasushi Akasaka , Kyoichi Suguro , Yoshitaka Tsunashima
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L21/823418 , H01L21/823437 , H01L21/823475 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823878 , H01L27/11 , H01L27/1104 , H01L29/1033 , H01L29/41775 , H01L29/41783 , H01L29/66545 , H01L29/78 , Y10S438/926
摘要： A method of manufacturing a semiconductor device according to this invention is characterized by including the steps of a) forming, on one major surface of a substrate, a gate structure constituted by either one of a dummy gate electrode and a gate electrode having an insulating film at least on bottom surface, and a device isolation insulating film so as to form a first groove divided by the dummy gate electrode or the gate electrode, to position the dummy gate electrode or the gate electrode in the first groove, and to form the gate structure to have an upper surface level not higher than an upper level of the device isolation insulating film, and b) forming source and drain electrodes in the first groove.
摘要翻译：根据本发明的制造半导体器件的方法的特征在于包括以下步骤：a）在衬底的一个主表面上形成由伪栅电极和具有绝缘膜的栅电极中的任一个构成的栅极结构至少在底表面上，以及器件隔离绝缘膜，以形成由伪栅电极或栅电极分隔的第一凹槽，以将伪栅电极或栅电极定位在第一凹槽中，并形成栅极结构具有不高于器件隔离绝缘膜的较高电平的上表面电平，以及b）在第一沟槽中形成源极和漏极。

4. 发明申请

US20070172997A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070172997A1
公开(公告)日：2007-07-26
申请号：US11715965
申请日：2007-03-09
申请人： Atsushi Yagishita , Kouji Matsuo , Yasushi Akasaka , Kyoichi Suguro , Yoshitaka Tsunashima
发明人： Atsushi Yagishita , Kouji Matsuo , Yasushi Akasaka , Kyoichi Suguro , Yoshitaka Tsunashima
IPC分类号： H01L21/8232
CPC分类号： H01L29/66575 , H01L21/823418 , H01L21/823437 , H01L21/823475 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823878 , H01L27/11 , H01L27/1104 , H01L29/1033 , H01L29/41775 , H01L29/41783 , H01L29/66545 , H01L29/78 , Y10S438/926
摘要： There is provided a semiconductor device including a substrate, a device isolation insulating film formed on the substrate, a gate electrode formed on the substrate, a gate wiring layer formed in the device isolation insulating film and connected to the gate electrode, source and drain electrodes arranged on the substrate to face each other via the gate electrode, and an insulating film covering bottom and side surfaces of each of the gate electrode and the gate wiring layer, wherein the gate, source and drain electrodes and gate wiring layer have upper surface levels equal to or lower than that of the device isolation insulating film.
摘要翻译：提供了一种半导体器件，包括衬底，在衬底上形成的器件隔离绝缘膜，形成在衬底上的栅电极，形成在器件隔离绝缘膜中并连接到栅电极的栅极布线层，源极和漏极布置在基板上，经由栅极电极相对对置;以及绝缘膜，其覆盖栅极电极和栅极布线层中的每一个的底部和侧面，其中栅极，源极和漏极以及栅极布线层具有上表面水平等于或低于器件绝缘膜的绝缘膜。

5. 发明申请

US20080224252A1 Semiconductor device having an element isolating insulating film 有权
标题翻译：具有元件隔离绝缘膜的半导体器件
公开(公告)号：US20080224252A1
公开(公告)日：2008-09-18
申请号：US12068635
申请日：2008-02-08
申请人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
发明人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
IPC分类号： H01L29/00
CPC分类号： H01L21/28194 , H01L21/28088 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/76262 , H01L21/823481 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545
摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.
摘要翻译：在使用外延生长方法选择性地在硅衬底上生长其上要形成元素的外延层时，形成外延层，以便在作为元件隔离绝缘膜的热氧化膜上方向上延伸，以防止形成小平面。随后，通过CMP去除外延层的不需要的部分以完成STI元件隔离结构。

6. 发明授权

US06989316B2 Semiconductor device and method for manufacturing 失效
公开(公告)号：US06989316B2
公开(公告)日：2006-01-24
申请号：US10406281
申请日：2003-04-04
申请人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
发明人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
IPC分类号： H01L21/20
CPC分类号： H01L21/28194 , H01L21/28088 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/76262 , H01L21/823481 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545
摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

7. 发明授权

US07772671B2 Semiconductor device having an element isolating insulating film 有权
标题翻译：具有元件隔离绝缘膜的半导体器件
公开(公告)号：US07772671B2
公开(公告)日：2010-08-10
申请号：US12068635
申请日：2008-02-08
申请人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
发明人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
IPC分类号： H01L29/00
CPC分类号： H01L21/28194 , H01L21/28088 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/76262 , H01L21/823481 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545
摘要： A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor element is formed on the semiconductor substrate and includes a gate electrode formed on the channel region of the projection via a gate insulating film. Source and drain regions are formed to pinch the channel region of the projection therebetween. A channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess. A top surface of the at least one projection is located higher than the top surface of the element isolating insulating film by 20 nm or more.
摘要翻译：一种半导体器件，包括在其表面上具有凹部的半导体衬底和形成在凹部中的至少一个突起。突起具有沟道区域，并且在凹部中形成元件隔离绝缘膜。 MIS半导体元件形成在半导体衬底上，并且包括通过栅极绝缘膜形成在突起的沟道区上的栅电极。形成源区和漏区以夹住其间的突起的沟道区。 MIS型半导体元件的沟道区域形成为经由凹部在其沟道宽度方向上到达位于与MIS型半导体元件相邻的至少一个突起。所述至少一个突起的顶表面比所述元件隔离绝缘膜的顶表面高20nm或更大。

8. 发明授权

US06376888B1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06376888B1
公开(公告)日：2002-04-23
申请号：US09559356
申请日：2000-04-27
申请人： Yoshitaka Tsunashima , Kyoichi Suguro , Atsushi Murakoshi , Kouji Matsuo , Toshihiko Iinuma
发明人： Yoshitaka Tsunashima , Kyoichi Suguro , Atsushi Murakoshi , Kouji Matsuo , Toshihiko Iinuma
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28088 , H01L21/28194 , H01L21/28202 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66553 , H01L29/66583
摘要： Disclosed is a semiconductor device having an N-type MIS transistor formed in a first region and a P-type MIS transistor formed in a second region, wherein, the N-type MIS transistor includes a first gate insulating film formed on at least the bottom of a first concave portion formed in the first region and a first gate electrode formed on the first gate insulating film, the P-type MIS transistor includes a second gate insulating film formed on at least the bottom of a second concave portion formed in the second region and a second gate electrode formed on the second gate insulating film, each of the first and second gate electrodes includes at least one metal-containing film, and at least one of the first and second gate electrodes is of a laminate structure including a plurality of the metal-containing films, and the work function of the metal-containing film constituting at least a part of the first gate electrode and in contact with the first gate insulating film is smaller than the work function of the metal-containing film constituting at least a part of the second gate electrode and in contact with the second gate insulating film.
摘要翻译：公开了一种半导体器件，其具有形成在第一区域中的N型MIS晶体管和形成在第二区域中的P型MIS晶体管，其中，所述N型MIS晶体管包括形成在至少底部的第一栅极绝缘膜形成在所述第一区域中的第一凹部和形成在所述第一栅极绝缘膜上的第一栅电极，所述P型MIS晶体管包括形成在所述第二栅极绝缘膜的至少第二凹部的底部上的第二栅极绝缘膜，区域和形成在所述第二栅极绝缘膜上的第二栅极电极，所述第一和第二栅极电极中的每一个包括至少一个含金属膜，并且所述第一和第二栅极电极中的至少一个是包括多个的含金属膜的膜，并且构成第一栅电极的至少一部分并与第一栅极绝缘膜接触的含金属膜的功函数小于th 构成至少一部分第二栅电极并与第二栅极绝缘膜接触的含金属膜的功函数。

9. 发明授权

US07972960B1 Method for manufacturing thin film 有权
标题翻译：薄膜制造方法
公开(公告)号：US07972960B1
公开(公告)日：2011-07-05
申请号：US12886240
申请日：2010-09-20
申请人： Kyoichi Suguro , Yoshitaka Tsunashima
发明人： Kyoichi Suguro , Yoshitaka Tsunashima
IPC分类号： H01L21/44
CPC分类号： H01L21/288 , H01L21/0243 , H01L21/02532 , H01L21/02601 , H01L21/02628 , H01L21/02639 , H01L21/76877 , H01L21/76879 , H01L21/76883
摘要： A method for manufacturing a thin film includes: applying a liquid to a surface of a processing target member having at least one of a trench and a concave portion. The liquid includes a solvent and at least one of fine particles of a metal, fine particles of a semiconductor, fine particles containing a metal oxide, and fine particles containing a semiconductor oxide. A first heat treatment is included for volatilizing the solvent of the liquid applied to the surface of the processing target member. The fine particles are remained on the surface of the processing target member. A second heat treatment is also included for heating the fine particles by using microwave irradiation. At least one of the trench and the concave portion is filled with the thin film containing the fine particles or a component of the fine particles.
摘要翻译：一种制造薄膜的方法包括：将液体施加到具有沟槽和凹部中的至少一个的处理目标构件的表面。该液体包括溶剂和金属微粒，半导体微粒，含有金属氧化物的微粒和含有半导体氧化物的微粒中的至少一种。包括第一次热处理以挥发施加到加工对象部件表面的液体的溶剂。微粒保留在加工对象构件的表面上。还包括通过使用微波照射来加热微粒的第二热处理。沟槽和凹部中的至少一个填充有含有细颗粒或细颗粒成分的薄膜。

10. 发明授权

US07041584B2 Method of manufacturing semiconductor device and the semiconductor device 失效
公开(公告)号：US07041584B2
公开(公告)日：2006-05-09
申请号：US10867765
申请日：2004-06-16
申请人： Masayuki Tanaka , Kazuaki Nakajima , Yoshitaka Tsunashima , Takayuki Ito , Kyoichi Suguro
发明人： Masayuki Tanaka , Kazuaki Nakajima , Yoshitaka Tsunashima , Takayuki Ito , Kyoichi Suguro
IPC分类号： H01L21/324 , H01L21/335
CPC分类号： H01L21/324 , H01L21/28518 , H01L21/32053 , H01L21/76843 , H01L21/76855 , H01L21/76864 , H01L21/76886 , H01L29/665
摘要： An aspect of the present invention provides a method of manufacturing a semiconductor device, including, forming an insulating film on a silicide layer formed at the surface of a silicon semiconductor substrate, etching the insulating film to form a contact hole in which the silicide layer is exposed, forming a metal nitride film on the bottom and side wall of the contact hole, carrying out a first heating process at 600° C. or lower on the substrate, carrying out, during the first heating process, a second heating process for 10 msec or shorter with light whose main wavelength is shorter than a light absorbing end of silicon, forming a contact conductor in the contact hole after the second heating process, and forming, on the insulating film, wiring that is electrically connected to the substrate through the contact conductor.

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