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1. 发明授权

US08159848B2 Power conversion circuit 有权
标题翻译：电源转换电路
公开(公告)号：US08159848B2
公开(公告)日：2012-04-17
申请号：US12598387
申请日：2008-12-11
申请人： Atsushi Morimoto , Matsuo Shiraishi , Kouichi Ishikawa , Tatsuo Morita , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Atsushi Morimoto , Matsuo Shiraishi , Kouichi Ishikawa , Tatsuo Morita , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H02M7/217
CPC分类号： H02M3/1582 , H02M7/219
摘要： A power conversion circuit includes a bidirectional switch 2. The bidirectional switch 2 has a first gate terminal G1, a second gate terminal G2, a first ohmic terminal S1 and a second ohmic terminal S2. The bidirectional switch 2 has four operation states. In the first state, the bidirectional switch 2 operates as a diode having a cathode as the first ohmic terminal S1 and an anode as the second ohmic terminal S2. In a second state, the bidirectional switch 2 operates as a diode having an anode as the first ohmic terminal S1 and a cathode as the second ohmic terminal S2. In a third state, the bidirectional switch 2 is bidirectionally conductive with via a diode between the first and second ohmic terminals S1 and S2. In a fourth state, the bidirectional switch 2 cuts off a bidirectional current between the first and second ohmic terminals.
摘要翻译：功率转换电路包括双向开关2.双向开关2具有第一栅极端子G1，第二栅极端子G2，第一欧姆端子S1和第二欧姆端子S2。双向开关2具有四个操作状态。在第一状态下，双向开关2作为具有阴极的第二欧姆端子S1和阳极作为第二欧姆端子S2的二极管工作。在第二状态下，双向开关2作为具有阳极的第二欧姆端子S1和阴极作为第二欧姆端子S2的二极管工作。在第三状态下，双向开关2通过第一和第二欧姆端子S1和S2之间的二极管双向导通。在第四状态下，双向开关2切断第一和第二欧姆端子之间的双向电流。

2. 发明授权

US08299737B2 Motor driving circuit 有权
标题翻译：电机驱动电路
公开(公告)号：US08299737B2
公开(公告)日：2012-10-30
申请号：US12596770
申请日：2008-12-02
申请人： Tatsuo Morita , Yasuhiro Uemoto , Tsuyoshi Tanaka , Matsuo Shiraishi , Atsushi Morimoto , Kouichi Ishikawa
发明人： Tatsuo Morita , Yasuhiro Uemoto , Tsuyoshi Tanaka , Matsuo Shiraishi , Atsushi Morimoto , Kouichi Ishikawa
IPC分类号： H02P6/14
CPC分类号： H02M7/53871 , H01L29/1066 , H01L29/2003 , H01L29/41758 , H01L29/7787 , H02P27/08
摘要： A motor driving circuit includes a three-phase inverter circuit 8, including three upper-arm switching elements 56a to 56c for driving upper arms of different phases of a three-phase motor 3, and three lower-arm switching elements 56d to 56f for driving lower arms of different phases. At least one of the upper-arm switching elements 56a to 56c and the lower-arm switching elements 56d to 56f is a semiconductor element that performs a diode operation. The diode operation is an operation in which a voltage less than or equal to a threshold voltage of a gate electrode G is applied to the gate electrode G with reference to a potential of a first ohmic electrode S, thereby conducting a current flow from the first ohmic electrode S to a second ohmic electrode D and blocking a current flow from the second ohmic electrode D to the first ohmic electrode S.
摘要翻译：电动机驱动电路包括三相逆变器电路8，其包括用于驱动三相电动机3的不同相的上臂的三个上臂开关元件56a至56c和用于驱动的三个下臂开关元件56d至56f 不同阶段的下臂。上臂开关元件56a至56c和下臂开关元件56d至56f中的至少一个是执行二极管操作的半导体元件。二极管操作是参照第一欧姆电极S的电位将小于或等于栅电极G的阈值电压的电压施加到栅电极G的操作，从而从第一欧姆电极S连接到第二欧姆电极D并阻塞从第二欧姆电极D到第一欧姆电极S的电流。

3. 发明申请

US20100135053A1 POWER CONVERSION CIRCUIT 有权
标题翻译：电源转换电路
公开(公告)号：US20100135053A1
公开(公告)日：2010-06-03
申请号：US12598387
申请日：2008-12-11
申请人： Atsushi Morimoto , Matsuo Shiraishi , Kouichi Ishikawa , Tatsuo Morita , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Atsushi Morimoto , Matsuo Shiraishi , Kouichi Ishikawa , Tatsuo Morita , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H02M7/217
CPC分类号： H02M3/1582 , H02M7/219
摘要： A power conversion circuit includes a bidirectional switch 2. The bidirectional switch 2 has a first gate terminal G1, a second gate terminal G2, a first ohmic terminal S1 and a second ohmic terminal S2. The bidirectional switch 2 has four operation states. In the first state, the bidirectional switch 2 operates as a diode having a cathode as the first ohmic terminal S1 and an anode as the second ohmic terminal S2. In a second state, the bidirectional switch 2 operates as a diode having an anode as the first ohmic terminal S1 and a cathode as the second ohmic terminal S2. In a third state, the bidirectional switch 2 is bidirectionally conductive with via a diode between the first and second ohmic terminals S1 and S2. In a fourth state, the bidirectional switch 2 cuts off a bidirectional current between the first and second ohmic terminals.
摘要翻译：功率转换电路包括双向开关2.双向开关2具有第一栅极端子G1，第二栅极端子G2，第一欧姆端子S1和第二欧姆端子S2。双向开关2具有四个操作状态。在第一状态下，双向开关2作为具有阴极的第二欧姆端子S1和阳极作为第二欧姆端子S2的二极管工作。在第二状态下，双向开关2作为具有阳极的第二欧姆端子S1和阴极作为第二欧姆端子S2的二极管工作。在第三状态下，双向开关2通过第一和第二欧姆端子S1和S2之间的二极管双向导通。在第四状态下，双向开关2切断第一和第二欧姆端子之间的双向电流。

4. 发明申请

US20100127652A1 MOTOR DRIVING CIRCUIT 有权
标题翻译：电机驱动电路
公开(公告)号：US20100127652A1
公开(公告)日：2010-05-27
申请号：US12596770
申请日：2008-12-02
申请人： Tatsuo Morita , Yasuhiro Uemoto , Tsuyoshi Tanaka , Matsuo Shiraishi , Atsushi Morimoto , Kouichi Ishikawa
发明人： Tatsuo Morita , Yasuhiro Uemoto , Tsuyoshi Tanaka , Matsuo Shiraishi , Atsushi Morimoto , Kouichi Ishikawa
IPC分类号： H02P6/14
CPC分类号： H02M7/53871 , H01L29/1066 , H01L29/2003 , H01L29/41758 , H01L29/7787 , H02P27/08
摘要： A motor driving circuit includes a three-phase inverter circuit 8, including three upper-arm switching elements 56a to 56c for driving upper arms of different phases of a three-phase motor 3, and three lower-arm switching elements 56d to 56f for driving lower arms of different phases. At least one of the upper-arm switching elements 56a to 56c and the lower-arm switching elements 56d to 56f is a semiconductor element that performs a diode operation. The diode operation is an operation in which a voltage less than or equal to a threshold voltage of a gate electrode G is applied to the gate electrode G with reference to a potential of a first ohmic electrode S, thereby conducting a current flow from the first ohmic electrode S to a second ohmic electrode D and blocking a current flow from the second ohmic electrode D to the first ohmic electrode S.
摘要翻译：电动机驱动电路包括三相逆变器电路8，其包括用于驱动三相电动机3的不同相的上臂的三个上臂开关元件56a至56c和用于驱动的三个下臂开关元件56d至56f 不同阶段的下臂。上臂开关元件56a至56c和下臂开关元件56d至56f中的至少一个是执行二极管操作的半导体元件。二极管操作是参照第一欧姆电极S的电位将小于或等于栅电极G的阈值电压的电压施加到栅电极G的操作，从而从第一欧姆电极S连接到第二欧姆电极D并阻塞从第二欧姆电极D到第一欧姆电极S的电流。

5. 发明申请

US20100097105A1 SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME 有权
标题翻译：半导体器件及其驱动方法
公开(公告)号：US20100097105A1
公开(公告)日：2010-04-22
申请号：US12445390
申请日：2007-11-20
申请人： Tatsuo Morita , Manabu Yanagihara , Hidetoshi Ishida , Yasuhiro Uemoto , Hiroaki Ueno , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Tatsuo Morita , Manabu Yanagihara , Hidetoshi Ishida , Yasuhiro Uemoto , Hiroaki Ueno , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H03B1/00 , H01L29/20 , H01L29/24 , H01L29/772 , H03K17/56
CPC分类号： H01L29/7787 , H01L27/0605 , H01L29/0619 , H01L29/1066 , H01L29/2003 , H01L29/432 , H01L29/739 , H01L29/8124
摘要： A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.
摘要翻译：半导体器件包括形成在衬底11上并具有沟道区的半导体层堆叠13，在半导体层叠层13上彼此隔开形成的第一电极16A和第二电极16B，形成在第一栅电极18A之间的第一栅电极18A 第一电极16A和第二电极16B，以及形成在第一栅电极18A和第二电极16B之间的第二栅电极18B。在半导体层堆叠13和第一栅电极18A之间形成具有p型导电性的第一控制层19A。

6. 发明授权

US08203376B2 Semiconductor device and method for driving the same 有权
标题翻译：半导体装置及其驱动方法
公开(公告)号：US08203376B2
公开(公告)日：2012-06-19
申请号：US12445390
申请日：2007-11-20
申请人： Tatsuo Morita , Manabu Yanagihara , Hidetoshi Ishida , Yasuhiro Uemoto , Hiroaki Ueno , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Tatsuo Morita , Manabu Yanagihara , Hidetoshi Ishida , Yasuhiro Uemoto , Hiroaki Ueno , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H03K17/687
CPC分类号： H01L29/7787 , H01L27/0605 , H01L29/0619 , H01L29/1066 , H01L29/2003 , H01L29/432 , H01L29/739 , H01L29/8124
摘要： A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.
摘要翻译：半导体器件包括形成在衬底11上并具有沟道区的半导体层堆叠13，在半导体层叠层13上彼此隔开形成的第一电极16A和第二电极16B，形成在第一栅电极18A之间的第一栅电极18A 第一电极16A和第二电极16B，以及形成在第一栅电极18A和第二电极16B之间的第二栅电极18B。在半导体层堆叠13和第一栅电极18A之间形成具有p型导电性的第一控制层19A。

7. 发明申请

US20120126290A1 NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：氮化物半导体器件及其制造方法
公开(公告)号：US20120126290A1
公开(公告)日：2012-05-24
申请号：US13360275
申请日：2012-01-27
申请人： Yasuhiro UEMOTO , Masahiro Hikita , Tetsuzo Ueda , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Yasuhiro UEMOTO , Masahiro Hikita , Tetsuzo Ueda , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L29/778
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/7783
摘要： A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.
摘要翻译：氮化物半导体器件包括：第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更宽的带隙的第二氮化物半导体层; 以及形成在所述第二氮化物半导体层上的第三氮化物半导体层。位于栅电极下方的第三氮化物半导体层的区域形成有具有p型导电性的控制区域，以及位于栅电极与源电极和漏极之间的第三氮化物半导体层的区域形成有具有比控制区域更高的电阻的高电阻区域。

8. 发明授权

US07910464B2 Method for manufacturing a semiconductor device having a III-V nitride semiconductor 有权
标题翻译：具有III-V族氮化物半导体的半导体器件的制造方法
公开(公告)号：US07910464B2
公开(公告)日：2011-03-22
申请号：US12695759
申请日：2010-01-28
申请人： Tomohiro Murata , Yutaka Hirose , Tsuyoshi Tanaka , Yasuhiro Uemoto
发明人： Tomohiro Murata , Yutaka Hirose , Tsuyoshi Tanaka , Yasuhiro Uemoto
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/66871 , H01L21/28 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/7787 , H01L29/8128
摘要： A semiconductor device of the present invention includes: a III-V nitride semiconductor layer including a channel region in which carriers travel; a concave portion provided in an upper portion of the channel region in the III-V nitride semiconductor layer; and a Schottky electrode consisting of a conductive material forming a Schottky junction with the semiconductor layer, and formed on a semiconductor layer, which spreads over the concave portion and peripheral portions of the concave portion, on the III-V nitride semiconductor layer. A dimension of the concave portion in a depth direction is set so that a portion of the Schottky electrode provided in the concave portion can adjust a quantity of the carriers traveling in the channel region.
摘要翻译：本发明的半导体器件包括：III-V族氮化物半导体层，其包括载流子行进的沟道区; 设置在III-V族氮化物半导体层中的沟道区的上部的凹部; 和由形成与半导体层形成肖特基结的导电材料构成的肖特基电极，形成在III-V族氮化物半导体层上的在凹部的凹部和周边部分上方扩散的半导体层上。深度方向上的凹部的尺寸被设定为使得设置在凹部中的肖特基电极的一部分可以调节在沟道区域中行进的载流子的量。

9. 发明授权

US07898002B2 Nitride semiconductor device and method for fabricating the same 有权
标题翻译：氮化物半导体器件及其制造方法
公开(公告)号：US07898002B2
公开(公告)日：2011-03-01
申请号：US11890480
申请日：2007-08-07
申请人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L21/337 , H01L21/335
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/432 , H01L29/66462
摘要： A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.
摘要翻译：氮化物半导体器件包括：衬底; 形成在所述基板上的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更大的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上并且包括具有至少单层结构的p型氮化物半导体的第三氮化物半导体层; 形成在所述第三氮化物半导体层上的栅极; 以及分别形成在位于栅电极两侧的区域中的源电极和漏电极。所述第三氮化物半导体层的厚度比所述栅极电极侧的部分的厚度大。

10. 发明申请

US20100327293A1 FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20100327293A1
公开(公告)日：2010-12-30
申请号：US12880704
申请日：2010-09-13
申请人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L29/20
CPC分类号： H01L29/7786 , H01L29/0843 , H01L29/1066 , H01L29/2003 , H01L29/432 , H01L29/66462 , H01L29/7783
摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.
摘要翻译：依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。栅电极与重掺杂的p型GaN层形成欧姆接触。源电极和漏电极设置在未掺杂的AlGaN层上。通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

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