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1. 发明授权

US08922029B2 Apparatus having a wiring board and memory devices 有权
标题翻译：具有接线板和存储器件的设备
公开(公告)号：US08922029B2
公开(公告)日：2014-12-30
申请号：US13363396
申请日：2012-02-01
申请人： Atsushi Hiraishi , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
发明人： Atsushi Hiraishi , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , G11C5/06 , G11C5/04 , G11C8/14 , H05K1/18
CPC分类号： G11C5/063 , G11C5/04 , G11C8/14 , H05K1/181 , H05K2201/09254 , H05K2201/09263 , H05K2201/10159 , Y02P70/611
摘要： An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.
摘要翻译：具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。

2. 发明授权

US08134239B2 Address line wiring structure and printed wiring board having same 有权
标题翻译：地址线路布线结构和具有该布线结构的印刷布线板
公开(公告)号：US08134239B2
公开(公告)日：2012-03-13
申请号：US12239900
申请日：2008-09-29
申请人： Atsushi Hiraishi , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
发明人： Atsushi Hiraishi , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： G11C5/063 , G11C5/04 , G11C8/14 , H05K1/181 , H05K2201/09254 , H05K2201/09263 , H05K2201/10159 , Y02P70/611
摘要： An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.
摘要翻译：具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。

3. 发明申请

US20090086522A1 ADDRESS LINE WIRING STRUCTURE AND PRINTED WIRING BOARD HAVING SAME 有权
标题翻译：地线接线结构和印刷线路板
公开(公告)号：US20090086522A1
公开(公告)日：2009-04-02
申请号：US12239900
申请日：2008-09-29
申请人： Atsushi HIRAISHI , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
发明人： Atsushi HIRAISHI , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
IPC分类号： G11C5/06 , H05K1/18 , H05K7/00
CPC分类号： G11C5/063 , G11C5/04 , G11C8/14 , H05K1/181 , H05K2201/09254 , H05K2201/09263 , H05K2201/10159 , Y02P70/611
摘要： An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.
摘要翻译：具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。

4. 发明授权

US07768867B2 Stacked semiconductor device 有权
标题翻译：堆叠半导体器件
公开(公告)号：US07768867B2
公开(公告)日：2010-08-03
申请号：US11761470
申请日：2007-06-12
申请人： Yoji Nishio , Yutaka Uematsu , Seiji Funaba , Hideki Osaka , Tsutomu Hara , Koichiro Aoki
发明人： Yoji Nishio , Yutaka Uematsu , Seiji Funaba , Hideki Osaka , Tsutomu Hara , Koichiro Aoki
IPC分类号： G11C8/00
CPC分类号： G11C7/02 , G11C5/02 , G11C5/04 , H01L25/105 , H01L2924/0002 , H01L2924/15311 , H01L2924/15331 , H01L2924/00
摘要： Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.
摘要翻译：叠层半导体器件包括多个存储器芯片，堆叠在一起，其中高速传输中的波形失真被去除。堆叠半导体器件1包括堆叠在一起的多个存储器芯片11,12。作为用于每周期两次输入/输出数据的控制信号的数据选通信号（DQS）和反相数据选通信号（/ DQS）被用作两个单端数据选通信号。数据选通信号和反相数据选通信号相互配合。用于数据选通信号L4的数据选通信号线连接到第一存储芯片11的数据选通信号（DQS）焊盘。用于/ DQS信号L5的反相数据选通信号线连接到第二存储芯片11的反相数据选通信号（/ DQS）焊盘存储芯片12。

5. 发明申请

US20080054379A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080054379A1
公开(公告)日：2008-03-06
申请号：US11675476
申请日：2007-02-15
申请人： Yoji Nishio , Yutaka Uematsu , Hideki Osaka , Tsutomu Hara , Seiji Funaba
发明人： Yoji Nishio , Yutaka Uematsu , Hideki Osaka , Tsutomu Hara , Seiji Funaba
IPC分类号： H01L29/94
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/109
摘要： Input circuit ensuring a noise margin for a reference voltage. A semiconductor chip 11a comprises a pad 14 that inputs a reference voltage Vref, an input circuit 13, a resistance element R1 connected between an input terminal of the input circuit 13 and the pad 14, a capacitance element C1 connected between the input terminal of the input circuit 13 and a power supply VDD, and a capacitance element C2 connected between the input terminal of the input circuit 13 and a ground VSS within the semiconductor chip. A resistance value of the resistance element R1 is set based on an impedance characteristic of a network, for supplying the reference voltage Vref.
摘要翻译：输入电路确保参考电压的噪声容限。半导体芯片11a包括输入参考电压Vref的焊盘14，连接在输入电路13的输入端子和焊盘14之间的电阻元件R 1，连接在输入端13之间的电容元件C 1 输入电路13的端子和电源VDD，以及连接在输入电路13的输入端子和半导体芯片内的接地VSS之间的电容元件C 2。基于网络的阻抗特性来设定电阻元件R 1的电阻值，用于提供基准电压Vref。

6. 发明申请

US20060249829A1 Stacked type semiconductor device 审中-公开
标题翻译：堆叠型半导体器件
公开(公告)号：US20060249829A1
公开(公告)日：2006-11-09
申请号：US11399608
申请日：2006-04-07
申请人： Mitsuaki Katagiri , Masanori Shibamoto , Tsutomu Hara , Koichiro Aoki , Naoya Kanda , Shuji Kikuchi , Hisashi Tanie
发明人： Mitsuaki Katagiri , Masanori Shibamoto , Tsutomu Hara , Koichiro Aoki , Naoya Kanda , Shuji Kikuchi , Hisashi Tanie
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L24/50 , H01L2225/06527 , H01L2225/06551 , H01L2225/06579 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/15311 , H01L2924/3011
摘要： A stacked type semiconductor device comprising: a baseboard having a terminal row formed at an end in which connecting terminals is arranged linearly and having a wiring pattern connected to the connecting terminals and external terminals; semiconductor chips having a pad row in which pads is arranged linearly in parallel to the terminal row and being stacked on the baseboard; and interposer boards having a wiring layer including a plurality of wires arranged in parallel with the same length for connecting between pads of the pad row and connecting terminals of the terminal row.
摘要翻译：一种叠层型半导体器件，包括：基板，其端部形成在端部，所述端子排连接端子线性布置，并且具有连接到所述连接端子和外部端子的布线图案; 具有垫排的半导体芯片，其中焊盘与端子排平行布置并且堆叠在基板上; 以及具有布线层的插入板，所述布线层包括以相同长度平行布置的多条布线，用于连接所述焊盘排的焊盘和所述端子排的连接端子。

7. 发明授权

US08641279B2 Packaging bag with fastener 有权
标题翻译：带紧固件的包装袋
公开(公告)号：US08641279B2
公开(公告)日：2014-02-04
申请号：US12293563
申请日：2007-02-09
申请人： Toru Ichikawa , Tsutomu Hara , Kazuhiro Umenaka
发明人： Toru Ichikawa , Tsutomu Hara , Kazuhiro Umenaka
IPC分类号： B65D33/16
CPC分类号： B65D75/008 , B65D33/2533 , B65D33/2541 , B65D75/5816
摘要： It is aimed to smoothly perform engagement and disengagement of a fastener of a packaging bag and easily take out an inner content by a desired amount. For these purposes, in a packaging bag 1 with a fastener 20 in which a male fastener element and a female fastener element are attached to inner surfaces of opposing flat surface portions 2a and an opening is opened or closed by engaging or disengaging both the fastener elements, pick-up tabs 40 are provided so as to project outward at a portion corresponding to a mounting portion of the fastener 20, or near the portion. The fastener is formed to be asymmetric with respect to the center thereof so that one side largely protruded is attached so as to be directed inward of the packaging bag.
摘要翻译：旨在顺利地执行包装袋的紧固件的接合和分离，并且容易地将内容物取出所需量。为了这些目的，在具有紧固件20的包装袋1中，通过使两个紧固件元件接合或脱开，打开或关闭在相对的平坦表面部分2a的内表面上连接有阳紧固件元件和阴紧固件元件拾取片40设置成在与紧固件20的安装部分对应的部分处或在该部分附近向外突出。紧固件形成为相对于其中心不对称，使得大的突出部分的一侧被安装成指向包装袋的内部。

8. 发明授权

US07904046B2 Radio equipment having an attenuator between antenna and radio module 失效
标题翻译：无线电设备在天线和无线电模块之间具有衰减器
公开(公告)号：US07904046B2
公开(公告)日：2011-03-08
申请号：US11785127
申请日：2007-04-16
申请人： Masaya Umemura , Yukihide Inagaki , Isao Takita , Tsutomu Hara
发明人： Masaya Umemura , Yukihide Inagaki , Isao Takita , Tsutomu Hara
IPC分类号： H04B15/00 , H04M1/00 , H04W4/00
CPC分类号： H04B1/40 , H04B1/109 , H04B1/52
摘要： A radio equipment, wherein an attenuator (10) is inserted between antennas (91, 92) and a radio module (2), and output and input sensitivities are raised and lowered simultaneously so as to keep the balance of a radio covering range with an input receiver coverage at a constant, and the antenna (91) and the antenna (92) with attenuator are switched over by a switch (8) to increase and decrease the radio coverage range and input receiver coverage while keeping the balance of the dynamic radio coverage range with the input receiver coverage.
摘要翻译：一种无线电设备，其中在天线（91,92）和无线电模块（2）之间插入衰减器（10），并且输出和输入灵敏度被同时升高和降低，以便将无线电覆盖范围的平衡保持为以恒定的输入接收机覆盖，并且具有衰减器的天线（91）和天线（92）由开关（8）切换，以增加和减少无线电覆盖范围并输入接收机覆盖，同时保持动态无线电的平衡覆盖范围与输入接收机覆盖范围。

9. 发明申请

US20050021810A1 Remote display protocol, video display system, and terminal equipment 审中-公开
标题翻译：远程显示协议，视频显示系统和终端设备
公开(公告)号：US20050021810A1
公开(公告)日：2005-01-27
申请号：US10651257
申请日：2003-08-29
申请人： Masaya Umemura , Tsutomu Hara , Kazushige Hiroi , Kazuo Shigematsu , Seishi Hanaoka
发明人： Masaya Umemura , Tsutomu Hara , Kazushige Hiroi , Kazuo Shigematsu , Seishi Hanaoka
IPC分类号： G06F15/16 , H04L29/06 , H04N7/14 , H04N7/173 , H04N21/2343 , H04N21/238 , H04N21/4385 , H04N21/4402
CPC分类号： H04N21/234309 , G06F3/1462 , G09G5/363 , G09G5/39 , H04N21/234363 , H04N21/4122 , H04N21/4126 , H04N21/42653 , H04N21/43637 , H04N21/440218 , H04N21/440263
摘要： In order to prevent a reduction in frame rate of a reproduced moving picture on the terminal equipment side for performing a display and enable moving picture playback under a simple construction in a remote display technology, either a server or a terminal equipment or both thereof are equipped with router-attached graphics engines. The server draws a window and decoration thereof into a virtual VRAM, calculates the difference in the drawn data, performs a first decode process as a pre-process, adds drawing position information to intermediate data obtained in the first decode process, and transmits moving picture stream data to the terminal equipment. The terminal equipment effects a second decode process used as a post-process on received data, and draws and displays the so-process data in accordance with the drawing position information.
摘要翻译：为了防止在终端设备侧再现运动图像的帧速率降低，用于执行显示，并且在远程显示技术中以简单的结构实现运动图像回放，或者是服务器或终端设备，或者它们都配备与路由器连接的图形引擎。服务器将窗口及其装饰画成虚拟VRAM，计算绘制数据的差异，执行第一解码处理作为预处理，将绘制位置信息添加到在第一解码处理中获得的中间数据，并发送运动图像将数据流传输到终端设备。终端设备对接收到的数据实施用作后处理的第二解码处理，并且根据绘图位置信息绘制和显示所谓的过程数据。

10. 发明授权

US6094674A Information processing system and information processing method and quality of service supplying method for use with the system 失效
标题翻译：信息处理系统和信息处理方法以及与系统一起使用的服务质量提供方法
公开(公告)号：US6094674A
公开(公告)日：2000-07-25
申请号：US106291
申请日：1998-06-29
申请人： Ryuichi Hattori , Toshihiko Ogura , Takashi Oeda , Koichi Okazawa , Hideki Osaka , Tsunehiro Tobita , Tsutomu Hara
发明人： Ryuichi Hattori , Toshihiko Ogura , Takashi Oeda , Koichi Okazawa , Hideki Osaka , Tsunehiro Tobita , Tsutomu Hara
IPC分类号： G06F15/00 , G06F9/50 , G06F11/32 , G06F12/00 , G06F13/00 , G06F13/368 , G06F15/16 , G06F15/173
CPC分类号： G06F9/5055 , G06F9/5044 , H04L12/26 , H04L29/12047 , H04L61/15 , H04L67/36 , G06F2209/5015
摘要： In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.
摘要翻译：在通过网络彼此连接的每个信息处理设备中，布置了其功能和性能被注册到其中的服务质量（QOS）表。当信息处理设备另外与网络链接时，其QOS表被自动地注册到网络的本地目录，使得代理将QOS表的内容转换成要经由用户界面提供给用户的服务信息。由于操作，连接到网络的每个信息处理设备的功能和性能的信息被转换成用户的服务信息。因此，用户可以更多地直接接收必要的服务。

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