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1. 发明授权

US6025620A Semiconductor device and method of producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US6025620A
公开(公告)日：2000-02-15
申请号：US53533
申请日：1998-04-02
申请人： Masatoshi Kimura , Hiroaki Sekikawa , Kaoru Motonami , Atsushi Amo
发明人： Masatoshi Kimura , Hiroaki Sekikawa , Kaoru Motonami , Atsushi Amo
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/72
CPC分类号： H01L27/10844 , H01L27/105 , H01L27/10852
摘要： In a semiconductor device having a DRAM memo cell and a peripheral circuit, source/drain regions of transistors composing the memory cell are not silicided to restrict a junction leak and to improve a refresh characteristic; surfaces of source/drain regions and gate electrodes of transistors composing the peripheral circuit are silicided to reduce resistance of contacts and resistance of wirings for enabling a high-speed operation; side walls made of insulating material are formed on sides of the gate electrodes of the transistor composing the peripheral circuit to serve as a mask when impurities are injected for forming the source/drain regions; and insulating material laminated in the memory cell serves as a mask against siliciding.
摘要翻译：在具有DRAM备忘单元和外围电路的半导体器件中，构成存储单元的晶体管的源极/漏极区域不被硅化以限制结漏电并提高刷新特性; 构成外围电路的晶体管的源极/漏极区域和栅极电极的表面被硅化，以降低接触电阻和用于实现高速操作的布线电阻; 在构成外围电路的晶体管的栅电极的侧面形成由绝缘材料制成的侧壁，作为用于形成源极/漏极区域的杂质的掩模，作为掩模; 并且层叠在存储单元中的绝缘材料用作防止硅化的掩模。

2. 发明授权

US06690053B2 Shared contact in a semiconductor device in which DRAMs and SRAMs are combined and method of manufacturing the same 有权
标题翻译：在其中组合DRAM和SRAM的半导体器件中的共享接触及其制造方法
公开(公告)号：US06690053B2
公开(公告)日：2004-02-10
申请号：US10162169
申请日：2002-06-05
申请人： Atsushi Amo , Masatoshi Kimura
发明人： Atsushi Amo , Masatoshi Kimura
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/10811 , H01L27/10897 , H01L27/11 , H01L27/1116 , Y10S257/903
摘要： The semiconductor device according to the present invention comprises side wall 9 formed over the sidewall of gate wiring 6 of a logic SRAM region, doped polysilicon 18 electrically connecting silicide layer 13 formed over the surface of diffused layer 11 and silicide layer 15 of gate wiring 6, W plug 26 electrically connecting doped polysilicon 18 and a first layer aluminum wiring, and W plug 25 electrically connecting the silicide layer over the surface of diffused layer 11 in the logic SRAM region and the first layer aluminum wiring.
摘要翻译：根据本发明的半导体器件包括形成在逻辑SRAM区域的栅极布线6的侧壁上的侧壁9，电连接形成在扩散层11的表面上的硅化物层13的掺杂多晶硅18和栅极布线6的硅化物层15 电连接掺杂多晶硅18的W插头26和第一层铝布线以及将硅化物层电连接在逻辑SRAM区域中的扩散层11的表面上的W插头25和第一层铝布线。

3. 发明申请

US20080179651A1 Semiconductor device including a TCAM having a storage element formed with a DRAM 失效
标题翻译：包括具有由DRAM形成的存储元件的TCAM的半导体器件
公开(公告)号：US20080179651A1
公开(公告)日：2008-07-31
申请号：US11882166
申请日：2007-07-31
申请人： Atsushi Amo , Shunji Kubo
发明人： Atsushi Amo , Shunji Kubo
IPC分类号： H01L27/108
CPC分类号： H01L27/10897 , G11C15/043 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/108
摘要： In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.
摘要翻译：为了提高从匹配线的电位的放电速度，半导体器件包括电容器，具有连接到电容器的存储节点的源极/漏极区域的存储晶体管，具有连接到存储器的栅电极的搜索晶体管以及连接匹配线和搜索晶体管的源极/漏极区域的堆叠接触。存储节点具有这样的配置，其中面向匹配线的存储节点的侧壁部分地从堆叠的接触件中退出，使得沿着匹配线的方向的平面图中的层叠接触件前面的侧壁的一部分位于比侧壁的剩余部分更远离堆叠的接触。

4. 发明授权

US07884480B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07884480B2
公开(公告)日：2011-02-08
申请号：US12186366
申请日：2008-08-05
申请人： Atsushi Hachisuka , Atsushi Amo , Tatsuo Kasaoka , Shunji Kubo
发明人： Atsushi Hachisuka , Atsushi Amo , Tatsuo Kasaoka , Shunji Kubo
IPC分类号： H01L23/48
CPC分类号： H01L27/10829 , H01L21/76807 , H01L21/76808 , H01L21/76838 , H01L21/76877 , H01L23/485 , H01L27/10811 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).
摘要翻译：提供了一种用于提高存储器和逻辑器件的半导体器件的性能的技术。半导体器件包括半导体衬底（1），半导体衬底（1）上的绝缘层（19），绝缘层（19）中的多个接触插塞（16,66）和绝缘层（30）其中形成电容器（82），多个接触插塞（25,75），阻挡金属层（27,87）和铜互连（29,88）。半导体衬底（1）的上表面中的源极/漏极区（9）与铜互连（29）电连接。在半导体衬底（1）的上表面中的相邻源极/漏极区域（59）中的一个电连接到铜互连（88），而另一个电连接到电容器（82）。

5. 发明申请

US20070059885A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070059885A1
公开(公告)日：2007-03-15
申请号：US11556269
申请日：2006-11-03
申请人： Atsushi Hachisuka , Atsushi Amo , Tatsuo Kasaoka , Shunji Kubo
发明人： Atsushi Hachisuka , Atsushi Amo , Tatsuo Kasaoka , Shunji Kubo
IPC分类号： H01L21/336
CPC分类号： H01L27/10829 , H01L21/76807 , H01L21/76808 , H01L21/76838 , H01L21/76877 , H01L23/485 , H01L27/10811 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).
摘要翻译：提供了一种用于提高存储器和逻辑器件的半导体器件的性能的技术。半导体器件包括半导体衬底（1），半导体衬底（1）上的绝缘层（19），绝缘层（19）中的多个接触插塞（16,66）和绝缘层（30）其中形成电容器（82），多个接触插塞（25,75），阻挡金属层（27,87）和铜互连（29,88）。半导体衬底（1）的上表面中的源极/漏极区（9）与铜互连（29）电连接。在半导体衬底（1）的上表面中的相邻源极/漏极区域（59）中的一个电连接到铜互连（88），而另一个电连接到电容器（82）。

6. 发明授权

US07145240B2 Semiconductor device having a capacitor and method of manufacturing the same 有权
标题翻译：具有电容器的半导体器件及其制造方法
公开(公告)号：US07145240B2
公开(公告)日：2006-12-05
申请号：US10370711
申请日：2003-02-24
申请人： Atsushi Hachisuka , Atsushi Amo , Tatsuo Kasaoka , Shunji Kubo
发明人： Atsushi Hachisuka , Atsushi Amo , Tatsuo Kasaoka , Shunji Kubo
IPC分类号： H01L23/48
CPC分类号： H01L27/10829 , H01L21/76807 , H01L21/76808 , H01L21/76838 , H01L21/76877 , H01L23/485 , H01L27/10811 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).
摘要翻译：提供了一种用于提高存储器和逻辑器件的半导体器件的性能的技术。半导体器件包括半导体衬底（1），半导体衬底（1）上的绝缘层（19），绝缘层（19）中的多个接触插塞（16,66）和绝缘层（30）其中形成电容器（82），多个接触插塞（25,75），阻挡金属层（27,87）和铜互连（29,88）。半导体衬底（1）的上表面中的源极/漏极区（9）与铜互连（29）电连接。在半导体衬底（1）的上表面中的相邻源极/漏极区域（59）中的一个电连接到铜互连（88），而另一个电连接到电容器（82）。

7. 发明授权

US07005694B2 Semiconductor device including a TCAM having a storage element formed with a DRAM 失效
公开(公告)号：US07005694B2
公开(公告)日：2006-02-28
申请号：US10890482
申请日：2004-07-14
申请人： Atsushi Amo , Shunji Kubo
发明人： Atsushi Amo , Shunji Kubo
IPC分类号： H01L27/108
CPC分类号： H01L27/10897 , G11C15/043 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/108
摘要： In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.

8. 发明授权

US08072074B2 Semiconductor device and method of manufacturing same 有权
公开(公告)号：US08072074B2
公开(公告)日：2011-12-06
申请号：US12975004
申请日：2010-12-21
申请人： Atsushi Hachisuka , Atsushi Amo , Tatsuo Kasaoka , Shunji Kubo
发明人： Atsushi Hachisuka , Atsushi Amo , Tatsuo Kasaoka , Shunji Kubo
IPC分类号： H01L23/48
CPC分类号： H01L27/10829 , H01L21/76807 , H01L21/76808 , H01L21/76838 , H01L21/76877 , H01L23/485 , H01L27/10811 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).

9. 发明申请

US20070246762A1 Semiconductor device including a TCAM having a storage element formed 失效
标题翻译：包括形成有存储元件的TCAM的半导体器件
公开(公告)号：US20070246762A1
公开(公告)日：2007-10-25
申请号：US11812870
申请日：2007-06-22
申请人： Atsushi Amo , Shunji Kubo
发明人： Atsushi Amo , Shunji Kubo
IPC分类号： H01L29/94
CPC分类号： H01L27/10897 , G11C15/043 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/108
摘要： In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.
摘要翻译：为了提高从匹配线的电位的放电速度，半导体器件包括电容器，具有连接到电容器的存储节点的源极/漏极区域的存储晶体管，具有连接到存储器的栅电极的搜索晶体管以及连接匹配线和搜索晶体管的源极/漏极区域的堆叠接触。存储节点具有这样的配置，其中面向匹配线的存储节点的侧壁部分地从堆叠的接触件中退出，使得沿着匹配线的方向的平面图中的层叠接触件前面的侧壁的一部分位于比侧壁的剩余部分更远离堆叠的接触。

10. 发明授权

US07563668B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07563668B2
公开(公告)日：2009-07-21
申请号：US11556269
申请日：2006-11-03
申请人： Atsushi Hachisuka , Atsushi Amo , Tatsuo Kasaoka , Shunji Kubo
发明人： Atsushi Hachisuka , Atsushi Amo , Tatsuo Kasaoka , Shunji Kubo
IPC分类号： H01L21/8242
CPC分类号： H01L27/10829 , H01L21/76807 , H01L21/76808 , H01L21/76838 , H01L21/76877 , H01L23/485 , H01L27/10811 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).
摘要翻译：提供了一种用于提高存储器和逻辑器件的半导体器件的性能的技术。半导体器件包括半导体衬底（1），半导体衬底（1）上的绝缘层（19），绝缘层（19）中的多个接触插塞（16,66）和绝缘层（30）其中形成电容器（82），多个接触插塞（25,75），阻挡金属层（27,87）和铜互连（29,88）。半导体衬底（1）的上表面中的源极/漏极区（9）与铜互连（29）电连接。在半导体衬底（1）的上表面中的相邻源极/漏极区域（59）中的一个电连接到铜互连（88），而另一个电连接到电容器（82）。

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