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1. 发明授权

US4706266A Dual mode-increment/decrement N-bit counter register 失效
标题翻译：双模增加/递减N位计数器寄存器
公开(公告)号：US4706266A
公开(公告)日：1987-11-10
申请号：US927308
申请日：1986-11-05
申请人： Asif Qayyum
发明人： Asif Qayyum
IPC分类号： H03K23/00 , H03K23/52 , H03K23/64 , H03K27/00 , H03K23/66
CPC分类号： H03K23/52
摘要： A counter cell for counting either up or down by one or two includes a multiplexer section, an increment/decrement section, and a carry section. The multiplexer section is responsive to control signals and input carry signals for generating a count signal which determines the counting by one or two. The increment/decrement section is responsive to count signal and an increment strobe signal for generating an incremented output signal and a decremented output signal. The carry section is responsive to the increment/decrement section and the input carry signals for generating a carryout-by-one signal and a carryout-by-two signal. A number of these counter cells are arrayed to form an N-bit counter.
摘要翻译：用于向上或向下计数一个或两个的计数器单元包括多路复用器部分，增量/减量部分和进位部分。复用器部分响应于控制信号和输入进位信号，用于产生一个计数信号，该计数信号确定计数一个或两个。增量/减量部分响应于计数信号和增量选通信号，用于产生递增的输出信号和递减的输出信号。进位部分响应于增量/减量部分和输入进位信号，用于产生进位逐一信号和进位逐个信号。这些计数器单元的数目被排列以形成N位计数器。

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