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1. 发明授权

US07565513B2 Processor with power saving reconfigurable floating point unit decoding an instruction to single full bit operation or multiple reduced bit operations 有权
标题翻译：具有省电可重配置浮点单元的处理器将指令解码为单个全位操作或多个减少位操作
公开(公告)号：US07565513B2
公开(公告)日：2009-07-21
申请号：US11680331
申请日：2007-02-28
申请人： Ashraf Ahmed , Kelvin Domnic Goveas , Michael Clark , Jelena Ilic
发明人： Ashraf Ahmed , Kelvin Domnic Goveas , Michael Clark , Jelena Ilic
IPC分类号： G06F9/302
CPC分类号： G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3017 , G06F9/30189 , G06F9/3836 , G06F9/384
摘要： A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into a single operation, when the full-bit mode is indicated, or multiple operations, when the reduced-bit mode is indicated.
摘要翻译：操作处理器的技术包括确定处理器的浮点单元（FPU）是否以全位模式或降低位模式操作。当指示缩小位模式时，指示被取出并且指示被解码为单个操作，当指示全位模式时，或多个操作。

2. 发明申请

US20080209185A1 Processor with reconfigurable floating point unit 审中-公开
标题翻译：具有可重构浮点单元的处理器
公开(公告)号：US20080209185A1
公开(公告)日：2008-08-28
申请号：US11756166
申请日：2007-05-31
申请人： Ashraf Ahmed , Kelvin Domnic Goveas , Michael Clark , Jelena Ilic
发明人： Ashraf Ahmed , Kelvin Domnic Goveas , Michael Clark , Jelena Ilic
IPC分类号： G06F7/38
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3013 , G06F9/30149 , G06F9/3017 , G06F9/30181 , G06F9/30189 , G06F9/382 , G06F9/384 , G06F9/3857 , G06F9/3885
摘要： A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into one or more full-bit operations, when the full-bit mode is indicated, or one or more reduced-bit operations, when the reduced-bit mode is indicated.
摘要翻译：操作处理器的技术包括确定处理器的浮点单元（FPU）是否以全位模式或降低位模式操作。当指示缩小位模式时，指令被取出并且当指示全位模式时，指令被解码为一个或多个全位操作，或者一个或多个精简位操作。

3. 发明申请

US20080209184A1 PROCESSOR WITH RECONFIGURABLE FLOATING POINT UNIT 有权
标题翻译：具有可重构浮动点单元的处理器
公开(公告)号：US20080209184A1
公开(公告)日：2008-08-28
申请号：US11680331
申请日：2007-02-28
申请人： Ashraf Ahmed , Kelvin Domnic Goveas , Michael Clark , Jelena Ilic
发明人： Ashraf Ahmed , Kelvin Domnic Goveas , Michael Clark , Jelena Ilic
IPC分类号： G06F9/00
CPC分类号： G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3017 , G06F9/30189 , G06F9/3836 , G06F9/384
摘要： A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into a single operation, when the full-bit mode is indicated, or multiple operations, when the reduced-bit mode is indicated.
摘要翻译：操作处理器的技术包括确定处理器的浮点单元（FPU）是否以全位模式或降低位模式操作。当指示缩小位模式时，指示被取出并且指示被解码为单个操作，当指示全位模式时，或多个操作。

4. 发明授权

US07464255B1 Using a shuffle unit to implement shift operations in a processor 有权
标题翻译：使用洗牌单元来实现处理器中的移位操作
公开(公告)号：US07464255B1
公开(公告)日：2008-12-09
申请号：US11192153
申请日：2005-07-28
申请人： Teik-Chung Tan , Kelvin Domnic Goveas
发明人： Teik-Chung Tan , Kelvin Domnic Goveas
IPC分类号： G06F15/00
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/30101 , G06F9/30167 , G06F9/30181
摘要： A method and mechanism for performing shift operations using a shuffle unit. A processor includes a shuffle unit configured to perform shuffle operations responsive to shuffle instructions. The shuffle unit is adapted to support shift operations as well. In response to determining a shuffle instruction is received, selected bits of an immediate value of the shuffle instruction are used to generate byte selects for relocating bytes of a source operand. In response to determining the instruction is a shift instruction, the shuffle unit performs an arithmetic operation on a first and second value, where the first value corresponds to a particular destination byte position, and the second value corresponds to the immediate value. The result of the arithmetic operation comprises a byte select which selects one of the bytes of a source operand for conveyance to the particular destination byte position. In the event a destination byte position should be cleared by the shift operation, the output for the particular destination byte position is forced to zero.
摘要翻译：一种用于使用混洗单元执行移位操作的方法和机构。处理器包括被配置为响应于随机播放指令执行随机播放操作的洗牌单元。洗牌单元也适用于支持换档操作。响应于确定接收到随机播放指令，使用随机播放指令的立即值的选定比特来产生用于重新定位源操作数的字节的字节选择。响应于确定指令是移位指令，混洗单元对第一和第二值执行算术运算，其中第一值对应于特定目的地字节位置，并且第二值对应于立即值。算术运算的结果包括字节选择，其选择用于传送到特定目的地字节位置的源操作数的字节之一。在通过移位操作清除目标字节位置的情况下，特定目的地字节位置的输出被强制为零。

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