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1. 发明授权

US07262095B1 System and method for reducing process-induced charging 有权
标题翻译：减少过程引发充电的系统和方法
公开(公告)号：US07262095B1
公开(公告)日：2007-08-28
申请号：US11146126
申请日：2005-06-07
申请人： Ashot Melik Martirosian , Zhizheng Liu , Mark Randolph
发明人： Ashot Melik Martirosian , Zhizheng Liu , Mark Randolph
IPC分类号： H01L21/336
CPC分类号： H01L21/76838 , H01L21/76816 , H01L27/11521
摘要： A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.
摘要翻译：半导体器件包括衬底，形成在衬底上的存储单元和与衬底的接触。接触形成在远离存储单元的区域中，起到提高衬底电位的作用。

2. 发明授权

US07626869B2 Multi-phase wordline erasing for flash memory 有权
标题翻译：闪存多相字线擦除
公开(公告)号：US07626869B2
公开(公告)日：2009-12-01
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

3. 发明授权

US08203178B2 System and method for reducing process-induced charging 有权
标题翻译：减少过程引发充电的系统和方法
公开(公告)号：US08203178B2
公开(公告)日：2012-06-19
申请号：US12860074
申请日：2010-08-20
申请人： Ashot Melik Martirosian , Zhizheng Liu , Mark Randolph
发明人： Ashot Melik Martirosian , Zhizheng Liu , Mark Randolph
IPC分类号： H01L21/336
CPC分类号： H01L21/76838 , H01L21/76816 , H01L27/11521
摘要： A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.
摘要翻译：半导体器件包括衬底，形成在衬底上的存储单元和与衬底的接触。接触形成在远离存储单元的区域中，起到提高衬底电位的作用。

4. 发明授权

US07804125B2 System and method for reducing process-induced charging 有权
标题翻译：减少过程引发充电的系统和方法
公开(公告)号：US07804125B2
公开(公告)日：2010-09-28
申请号：US11782507
申请日：2007-07-24
申请人： Ashot Melik Martirosian , Zhizheng Liu , Mark Randolph
发明人： Ashot Melik Martirosian , Zhizheng Liu , Mark Randolph
IPC分类号： H01L21/336
CPC分类号： H01L21/76838 , H01L21/76816 , H01L27/11521
摘要： A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.
摘要翻译：半导体器件包括衬底，形成在衬底上的存储单元和与衬底的接触。接触形成在远离存储单元的区域中，起到提高衬底电位的作用。

5. 发明授权

US07561457B2 Select transistor using buried bit line from core 有权
标题翻译：选择晶体管使用埋入位线从核心
公开(公告)号：US07561457B2
公开(公告)日：2009-07-14
申请号：US11465701
申请日：2006-08-18
申请人： Mark Randolph , Zhizheng Liu , Ashot Melik-Martirosian , Yi He , Shankar Sinha
发明人： Mark Randolph , Zhizheng Liu , Ashot Melik-Martirosian , Yi He , Shankar Sinha
IPC分类号： G11C17/00
CPC分类号： G11C5/063 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in the core memory array and with substantially the same channel length.
摘要翻译：半导体器件包括核心存储器阵列和周边区域。核心存储器阵列区域包括一组存储器单元。外围区域包括一组选择晶体管。选择晶体管以与芯存储器阵列中的存储器单元基本相同的间距形成并具有基本上相同的沟道长度。

6. 发明申请

US20080279014A1 MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY 有权
标题翻译：闪存存储器的多相WORDLINE擦除
公开(公告)号：US20080279014A1
公开(公告)日：2008-11-13
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

7. 发明授权

US07746698B2 Programming in memory devices using source bitline voltage bias 有权
标题翻译：使用源位线电压偏置对存储器件进行编程
公开(公告)号：US07746698B2
公开(公告)日：2010-06-29
申请号：US11956032
申请日：2007-12-13
申请人： Zhizheng Liu , An Chen , Wei Zheng , Kuo-Tung Chang , Sung-Yong Chung , Gulzar Ahmed Kathawala , Ashot Melik-Martirosian
发明人： Zhizheng Liu , An Chen , Wei Zheng , Kuo-Tung Chang , Sung-Yong Chung , Gulzar Ahmed Kathawala , Ashot Melik-Martirosian
IPC分类号： G11C16/04
CPC分类号： G11C16/0491 , G11C16/12
摘要： Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.
摘要翻译：提出了有助于改进非易失性存储器（例如闪速存储器）中的编程存储器单元的系统和方法。优化的电压分量可以有助于在诸如编程操作的操作期间向与存储器单元相关联的源极，漏极和栅极提供相应的电压。优化的电压分量可以有助于在单元的编程期间向存储器单元提供预定的源位线电压，以便于减少与位线相关联的泄漏电流，这可以改善存储器单元的编程，并且有助于减少编程电流，导致功率有效的编程和改进的编程速度。

8. 发明申请

US20090154246A1 PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS 有权
标题翻译：使用源电压偏置在存储器件中编程
公开(公告)号：US20090154246A1
公开(公告)日：2009-06-18
申请号：US11956032
申请日：2007-12-13
申请人： Zhizheng Liu , An Chen , Wei Zheng , Kuo-Tung Chang , Sung-Yong Chung , Gulzar Ahmed Kathawala , Ashot Melik-Martirosian
发明人： Zhizheng Liu , An Chen , Wei Zheng , Kuo-Tung Chang , Sung-Yong Chung , Gulzar Ahmed Kathawala , Ashot Melik-Martirosian
IPC分类号： G11C16/04
CPC分类号： G11C16/0491 , G11C16/12
摘要： Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.
摘要翻译：提出了有助于改进非易失性存储器（例如闪速存储器）中的编程存储器单元的系统和方法。优化的电压分量可以有助于在诸如编程操作的操作期间向与存储器单元相关联的源极，漏极和栅极提供相应的电压。优化的电压分量可以有助于在单元的编程期间向存储器单元提供预定的源位线电压，以便于减少与位线相关联的泄漏电流，这可以改善存储器单元的编程，并且有助于减少编程电流，导致功率有效的编程和改进的编程速度。

9. 发明申请

US20060291282A1 Flash memory cell and methods for programming and erasing 有权
公开(公告)号：US20060291282A1
公开(公告)日：2006-12-28
申请号：US11511763
申请日：2006-08-29
申请人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
发明人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
IPC分类号： G11C11/34
CPC分类号： G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/66833
摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

10. 发明申请

US20060268593A1 Read-only memory array with dielectric breakdown programmability 审中-公开
标题翻译：具有介电击穿可编程性的只读存储阵列
公开(公告)号：US20060268593A1
公开(公告)日：2006-11-30
申请号：US11136981
申请日：2005-05-25
申请人： Meng Ding , Zhizheng Liu , Yi He , Mark Randolph
发明人： Meng Ding , Zhizheng Liu , Yi He , Mark Randolph
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C2213/72 , H01L27/1021 , H01L27/112 , H01L27/11206 , H01L27/118
摘要： According to one exemplary embodiment, a programmable ROM array includes at least one bitline situated in a substrate. The programmable ROM array further includes at least one wordline situated over the at least one bitline. The programmable ROM array further includes a memory cell situated at an intersection of the at least one bitline and the at least one wordline, where the memory cell includes a dielectric region situated between the at least one bitline and the at least one wordline. A programming operation causes the memory cell to change from a first logic state to a second logic state by causing the dielectric region to break down. The programming operation causes the memory cell to operate as a diode. A resistance of the memory cell can be measured in a read operation to determine if the memory cell has the first or second logic state.
摘要翻译：根据一个示例性实施例，可编程ROM阵列包括位于衬底中的至少一个位线。可编程ROM阵列还包括位于至少一个位线上的至少一个字线。可编程ROM阵列还包括位于所述至少一个位线和所述至少一个字线的交叉点处的存储器单元，其中所述存储器单元包括位于所述至少一个位线和所述至少一个字线之间的电介质区域。通过使介电区域分解，编程操作使存储单元从第一逻辑状态变为第二逻辑状态。编程操作使存储单元作为二极管工作。可以在读取操作中测量存储器单元的电阻，以确定存储单元是否具有第一或第二逻辑状态。

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