专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07026217B1 Method of forming an antifuse on a semiconductor substrate using wet oxidation of a nitrided substrate 失效
标题翻译：在氮化衬底的湿氧化下在半导体衬底上形成反熔丝的方法
公开(公告)号：US07026217B1
公开(公告)日：2006-04-11
申请号：US10697446
申请日：2003-10-29
申请人： Arvind Kamath , Venkatesh P. Gopinath , Wen-Chin Yeh , David Pachura
发明人： Arvind Kamath , Venkatesh P. Gopinath , Wen-Chin Yeh , David Pachura
IPC分类号： H01L21/336
CPC分类号： H01L21/31662 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/28211 , H01L21/2822 , H01L21/28238 , H01L21/76224 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method of producing an antifuse includes introducing nitrogen by ion implantation means into the substrate. An oxide dielectric layer is then formed on the nitrided substrate in a wet oxidation ambient. The conditions of the ion implantation and the oxidation are controlled to generate a dielectric with uniform thickness and a low breakdown voltage when subjected to a high electric field.
摘要翻译：制造反熔丝的方法包括通过离子注入装置将氮引入衬底。然后在湿氧化环境中在氮化衬底上形成氧化物介电层。控制离子注入和氧化的条件以产生具有均匀厚度的电介质和当受到高电场时的低击穿电压。

2. 发明授权

US07619294B1 Shallow trench isolation structure with low trench parasitic capacitance 失效
标题翻译：浅沟槽隔离结构具有低沟槽寄生电容
公开(公告)号：US07619294B1
公开(公告)日：2009-11-17
申请号：US11262173
申请日：2005-10-28
申请人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
发明人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
摘要翻译：提供了用于在集成电路基板上形成隔离结构的方法和组合物。首先，在集成电路基板中蚀刻沟槽。然后在沟槽中形成下介电层，使得下电介质层至少部分地填充沟槽。然后在下介电层上形成上电介质层以产生隔离结构，上电介质层和下电介质层一起具有小于二氧化硅的有效介电常数，从而实现与隔离结构相关联的电容要减少

3. 发明授权

US06586814B1 Etch resistant shallow trench isolation in a semiconductor wafer 失效
标题翻译：在半导体晶片中进行耐腐蚀浅沟槽隔离
公开(公告)号：US06586814B1
公开(公告)日：2003-07-01
申请号：US09735084
申请日：2000-12-11
申请人： Rajiv Patel , David Chan , Arvind Kamath , Ken Rafftesaeth , Venkatesh P. Gopinath
发明人： Rajiv Patel , David Chan , Arvind Kamath , Ken Rafftesaeth , Venkatesh P. Gopinath
IPC分类号： H01L2900
CPC分类号： H01L21/76224
摘要： A shallow isolating trench is formed in a semiconductor wafer between active component areas to electrically isolate the active components from each other. The isolating trench is primarily formed of an insulating material, such as an oxide, in a recess formed into the wafer. An etch resistant material, such as BTBAS nitride, is placed over the insulating material in the recess. The etch resistant material protects the insulating material from erosion due to subsequent semiconductor fabrication process steps, so the integrity of the isolating trench and the planarity of the wafer are generally maintained.
摘要翻译：在活性组分区域之间的半导体晶片中形成浅隔离沟槽，以将活性组分彼此电隔离。隔离沟槽主要由形成在晶片中的凹部中的绝缘材料（例如氧化物）形成。诸如BTBAS氮化物的耐蚀刻材料放置在凹槽中的绝缘材料上。耐蚀刻材料保护绝缘材料免受由于随后的半导体制造工艺步骤的侵蚀，因此通常保持隔离沟槽的完整性和晶片的平面性。

4. 发明授权

US06569739B1 Method of reducing the effect of implantation damage to shallow trench isolation regions during the formation of variable thickness gate layers 有权
标题翻译：在形成可变厚度栅极层期间减少对浅沟槽隔离区的注入损伤的影响的方法
公开(公告)号：US06569739B1
公开(公告)日：2003-05-27
申请号：US10216425
申请日：2002-08-08
申请人： Arvind Kamath , Venkatesh P. Gopinath
发明人： Arvind Kamath , Venkatesh P. Gopinath
IPC分类号： H01L21336
CPC分类号： H01L21/823462 , H01L21/26506 , H01L21/76237 , H01L21/823481
摘要： Embodiments of the invention include a method for blanket ion implanting a semiconductor substrate surface to induce uniform damage over desired portions of the surface thereby reducing non-uniform etch effects caused by the varying etch rates of surface materials and conditions during surface cleaning. The invention includes providing a semiconductor substrate having gate oxide regions and a sacrificial oxide layer of a predetermined thickness formed thereon. The surface of the substrate is pattern masked to reveal openings in the gate oxide regions and ion implanted through the openings in the pattern mask to form gate oxide regions. The pattern mask is removed from the substrate and a blanket implantation of the sacrificial oxide layer is performed. The substrate is then cleaned to remove the sacrificial oxide layer leaving the substrate in readiness for further processing.
摘要翻译：本发明的实施例包括用于覆盖离子注入半导体衬底表面以在表面的所需部分上引起均匀损伤的方法，从而减少由表面材料的变化蚀刻速率和表面清洁期间的条件引起的不均匀的蚀刻效应。本发明包括提供具有形成在其上的预定厚度的栅极氧化物区域和牺牲氧化物层的半导体衬底。衬底的表面被图案掩模以露出栅极氧化物区域中的开口，并且通过图案掩模中的开口注入离子以形成栅极氧化物区域。从衬底去除图案掩模，并执行牺牲氧化物层的覆盖注入。然后清洁衬底以除去离开衬底的牺牲氧化物层以备进一步处理。

5. 发明授权

US08021955B1 Method characterizing materials for a trench isolation structure having low trench parasitic capacitance 有权
标题翻译：用于具有低沟槽寄生电容的沟槽隔离结构的方法表征材料
公开(公告)号：US08021955B1
公开(公告)日：2011-09-20
申请号：US12574426
申请日：2009-10-06
申请人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
发明人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.
摘要翻译：提供了用于在集成电路基板上形成多层隔离结构的方法和组合物。工艺可以包括为下电介质层选择下电介质材料，并选择用于上电介质层的上电介质材料。选择对应于下部和上部介电材料的厚度的一系列有效介电常数。下介电层和上电介质层中的每一个的厚度范围由可接受的介电常数的范围决定，使用表示与下部上部电介质层的材料的厚度对应的有效介电常数的信息，能够形成多层电介质层，层隔离结构。

6. 发明授权

US07001823B1 Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance 有权
标题翻译：制造具有低沟槽寄生电容的浅沟槽隔离结构的方法
公开(公告)号：US07001823B1
公开(公告)日：2006-02-21
申请号：US09991202
申请日：2001-11-14
申请人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
发明人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
摘要翻译：提供了用于在集成电路基板上形成隔离结构的方法和组合物。首先，在集成电路基板中蚀刻沟槽。然后在沟槽中形成下介电层，使得下电介质层至少部分地填充沟槽。然后在下介电层上形成上电介质层以产生隔离结构，上电介质层和下电介质层一起具有小于二氧化硅的有效介电常数，从而实现与隔离结构相关联的电容要减少

7. 发明授权

US06812158B1 Modular growth of multiple gate oxides 有权
标题翻译：多栅极氧化物的模块生长
公开(公告)号：US06812158B1
公开(公告)日：2004-11-02
申请号：US10335177
申请日：2002-12-31
申请人： Wen-Chin Yeh , Venkatesh Gopinath , Arvind Kamath
发明人： Wen-Chin Yeh , Venkatesh Gopinath , Arvind Kamath
IPC分类号： H01L2131
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31658 , H01L21/823462 , H01L21/823481 , Y10S438/981
摘要： Growth of multiple gate oxides. By implanting different sites of a wafer with different doses of an oxide growth retardant, the entire wafer can grow oxides of different thicknesses even after being exposed to the same oxidation environment. The process is modular insofar as the implantation of one site has no effect on rate of growth of other sites.
摘要翻译：多栅极氧化物的生长。通过用不同剂量的氧化物生长阻滞剂植入晶片的不同位置，即使在暴露于相同的氧化环境之后，整个晶片也可以生长不同厚度的氧化物。该过程是模块化的，因为一个位点的植入对其他位点的生长速率没有影响。

8. 发明授权

US08796774B2 Printed non-volatile memory 有权
标题翻译：打印的非易失性存储器
公开(公告)号：US08796774B2
公开(公告)日：2014-08-05
申请号：US13585673
申请日：2012-08-14
申请人： Arvind Kamath , Patrick Smith , James Montague Cleeves
发明人： Arvind Kamath , Patrick Smith , James Montague Cleeves
IPC分类号： H01L29/66 , H01L29/788
CPC分类号： H01L21/28518 , H01L21/288 , H01L21/76801 , H01L21/76895 , H01L27/115 , H01L27/11558 , H01L27/1292 , H01L29/66757 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.
摘要翻译：公开了一种非易失性存储单元，其具有位于相同水平位置并且间隔开预定距离的第一和第二半岛，所述第一半岛具有提供控制栅极和所述第二半岛岛提供源极和漏极端子; 在所述第一半导体岛的至少一部分上的栅介质层; 在所述第二半导体岛的至少一部分上的隧道介电层; 至少部分栅极电介质层和隧道电介质层上的浮栅; 以及与控制栅极以及源极和漏极端子电接触的金属层。在一个有利的实施例中，可以使用“全印刷”工艺技术来制造非易失性存储单元。

9. 发明申请

US20140094004A1 Printed Dopant Layers 有权
标题翻译：印刷掺杂层
公开(公告)号：US20140094004A1
公开(公告)日：2014-04-03
申请号：US13633816
申请日：2012-10-02
申请人： Arvind Kamath , James Montague Cleeves , Joerg Rockenberger , Patrick Smith , Fabio Zürcher
发明人： Arvind Kamath , James Montague Cleeves , Joerg Rockenberger , Patrick Smith , Fabio Zürcher
IPC分类号： H01L21/336
CPC分类号： H01L27/1292 , H01L29/66757
摘要： A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.
摘要翻译：一种用于制造诸如MOS晶体管的电子器件的方法，包括以下步骤：在电功能衬底上形成多个半导体岛，在第一半导体岛子集上或第二子体上印刷第一介电层，在半导体岛的第二子集上或之上，以及退火。第一介电层包含第一掺杂剂，并且（任选的）第二介电层包含不同于第一掺杂剂的第二掺杂剂。电介质层，半导体岛和衬底被充分退火以将第一掺杂剂扩散到半导体岛的第一子集中，并且当存在时将第二掺杂剂扩散到半导体岛的第二子集中。

10. 发明授权

US08426905B2 Profile engineered, electrically active thin film devices 有权
标题翻译：型材设计，电活性薄膜器件
公开(公告)号：US08426905B2
公开(公告)日：2013-04-23
申请号：US12243880
申请日：2008-10-01
申请人： Arvind Kamath , Erik Scher , Patrick Smith , Aditi Chandra , Steven Molesa
发明人： Arvind Kamath , Erik Scher , Patrick Smith , Aditi Chandra , Steven Molesa
IPC分类号： H01L29/788
CPC分类号： H01L21/36 , C23C18/08 , C23C18/122 , C23C18/1245 , C23C18/1295 , H01L21/02532 , H01L21/02601 , H01L21/02628 , H01L21/28273 , H01L21/28518 , H01L21/288 , H01L21/76871 , H01L21/76895 , H01L27/1285 , H01L27/1292 , H01L28/40 , H01L29/0657 , H01L29/66143 , H01L29/6675 , H01L29/7881 , H01L29/872 , H05K1/16 , H05K1/162 , H05K3/125 , H05K2201/098
摘要： The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.
摘要翻译：本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许随后沉积的结构的更完整的阶梯覆盖。本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式