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1. 发明申请

US20090245192A1 Reconfigurable Wireless Modem Sub-Circuits To Implement Multiple Air Interface Standards 有权
标题翻译：可重构无线调制解调器子电路实现多个空中接口标准
公开(公告)号：US20090245192A1
公开(公告)日：2009-10-01
申请号：US12396270
申请日：2009-03-02
申请人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Ali Rostampisheh , Raghu Challa , Hamanth Sampath , Min Wu , Joseph Zanotelli , Mrinal M. Nath
发明人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Ali Rostampisheh , Raghu Challa , Hamanth Sampath , Min Wu , Joseph Zanotelli , Mrinal M. Nath
IPC分类号： H04W88/16 , G06F9/46
CPC分类号： G06F15/7842
摘要： A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.
摘要翻译：灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。子电路的任务管理器可以配置和控制子电路的可配置硬件。中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。每个任务列表包括相应子电路的任务指令。子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

2. 发明授权

US08572332B2 De-interleaving mechanism involving a multi-banked LLR buffer 有权
标题翻译：涉及多段LLR缓冲器的解交织机制
公开(公告)号：US08572332B2
公开(公告)日：2013-10-29
申请号：US12404613
申请日：2009-03-16
申请人： Ali RostamPisheh , Raghu N. Challa , Iwen Yao , Davie J. Santos , Mrinal M. Nath
发明人： Ali RostamPisheh , Raghu N. Challa , Iwen Yao , Davie J. Santos , Mrinal M. Nath
IPC分类号： G06F12/00
CPC分类号： H03M13/2785 , H03M13/2764 , H03M13/2771 , H03M13/2775 , H03M13/6566
摘要： A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.
摘要翻译：解交织器产生多个解交织重排物理（DRP）地址，以将对应的多个LLR值同时写入多存储存储器，使得不多于一个LLR值被写入多存储体的每个存储体一次记忆这种并行写入的序列导致存储在存储器中的子包的传输的LLR值。在生成DRP地址期间执行的地址转换导致LLR值被存储在存储体中，使得解码器可以以解交织的顺序读出存储器中的LLR值。存储体的每个存储器位置是用于存储多个相关LLR值的字位置，其中一个LLR值与其奇偶校验值一起存储。用于同时写入多个LLR值的能力用于以快速有效的方式清除位置。

3. 发明申请

US20090249134A1 DE-INTERLEAVING MECHANISM INVOLVING A MULTI-BANKED LLR BUFFER 有权
标题翻译：涉及多银行LLR缓冲区的交互机制
公开(公告)号：US20090249134A1
公开(公告)日：2009-10-01
申请号：US12404613
申请日：2009-03-16
申请人： Ali RostamPisheh , Raghu N. Challa , Iwen Yao , Davie J. Santos , Mrinal M. Nath
发明人： Ali RostamPisheh , Raghu N. Challa , Iwen Yao , Davie J. Santos , Mrinal M. Nath
IPC分类号： G11C29/00 , G06F12/02
CPC分类号： H03M13/2785 , H03M13/2764 , H03M13/2771 , H03M13/2775 , H03M13/6566
摘要： A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.
摘要翻译：解交织器生成多个解交织重排物理（DRP）地址，以将对应的多个LLR值同时写入多存储存储器，使得不多于一个LLR值被写入多存储体的每个存储体一次记忆这种并行写入的序列导致存储在存储器中的子包的传输的LLR值。在生成DRP地址期间执行的地址转换导致LLR值被存储在存储体中，使得解码器可以以解交织的顺序读出存储器中的LLR值。存储体的每个存储器位置是用于存储多个相关LLR值的字位置，其中一个LLR值与其奇偶校验值一起存储。用于同时写入多个LLR值的能力用于以快速有效的方式清除位置。

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