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1. 发明授权

US07466252B1 Method and apparatus for calibrating a scaled current electronic circuit 有权
标题翻译：用于校准缩放的当前电子电路的方法和装置
公开(公告)号：US07466252B1
公开(公告)日：2008-12-16
申请号：US11827533
申请日：2007-07-12
申请人： Georgi I. Radulov , Patrick J. Quinn , Johannes A. Hegt , Arthur H. M. van Roermund
发明人： Georgi I. Radulov , Patrick J. Quinn , Johannes A. Hegt , Arthur H. M. van Roermund
IPC分类号： H03M1/10
CPC分类号： H03M1/1061 , H03M1/687 , H03M1/745 , H03M1/747
摘要： A method and apparatus for the calibration of current cells, whereby a current signal from each current cell may be generated by either a thermometer current cell, or a binary current cell. If generated by a binary current cell, then two or more replica binary current cells exist to form a group of binary current cells within two or more binary current cell sets. The current magnitude generated by each replica current cell of each binary current cell group is first calibrated to be substantially equal to each other. Next, the combined current generated by the replica current cell group is calibrated to be substantially equal to a magnitude of a temporary current signal, or a portion thereof. Subsequent less-significant binary current cell groups are similarly calibrated to the temporary current signal through the use of the previously calibrated, more-significant binary current cell groups.
摘要翻译：用于校准当前单元的方法和装置，由此可以由温度计电流单元或二进制电流单元产生来自每个当前单元的电流信号。如果由二进制当前单元生成，则存在两个或多个复制二进制当前单元以在两个或更多个二进制当前单元组内形成一组二进制当前单元。每个二进制当前单元组的每个复制当前单元产生的电流幅度首先被校准为彼此基本相等。接下来，由复制当前小区组生成的组合电流被校准为基本上等于临时电流信号或其一部分的大小。通过使用先前校准的更重要的二进制当前小区组，随后的较不重要的二进制当前小区组被类似地校准为临时电流信号。

2. 发明授权

US07076384B1 Method and apparatus for calibrating a current-based circuit 有权
标题翻译：用于校准基于电流的电路的方法和装置
公开(公告)号：US07076384B1
公开(公告)日：2006-07-11
申请号：US10955808
申请日：2004-09-29
申请人： Georgi I Radulov , Patrick J. Quinn , Johannes A. Hegt , Arthur H. M. van Roermund
发明人： Georgi I Radulov , Patrick J. Quinn , Johannes A. Hegt , Arthur H. M. van Roermund
IPC分类号： G01R35/00
CPC分类号： H03M1/1057 , H03M1/687 , H03M1/745 , H03M1/747
摘要： A method and apparatus for calibrating a current source to a reference current through the use of 1-bit current comparisons. A temporary current source is first calibrated to the reference current, which allows an input offset current generated by the current comparator to be memorized. The current to be calibrated is then fine-tuned to the temporary current within specified limits, which effectively cancels comparison error that is generated by the input offset current.
摘要翻译：一种通过使用1位电流比较将电流源校准为参考电流的方法和装置。临时电流源首先被校准到参考电流，这允许存储当前比较器产生的输入偏移电流。然后将要校准的电流微调到指定限制内的临时电流，这有效地消除了由输入偏移电流产生的比较误差。

3. 发明授权

US4443885A Charge transfer method and device for carrying out the method 失效
标题翻译：电荷转移方法及实施方法的装置
公开(公告)号：US4443885A
公开(公告)日：1984-04-17
申请号：US425148
申请日：1982-09-28
申请人： Arthur H. M. van Roermund
发明人： Arthur H. M. van Roermund
IPC分类号： H01L21/339 , G11C19/18 , G11C27/04 , H01L29/762 , G11C19/28 , H01L29/78 , H03K3/353
CPC分类号： G11C27/04 , G11C19/186
摘要： A method and device in which both positive and negative signal charges can be transferred from a first capacitance to a first point via a transistor circuit which exhibits a threshold level. For this purpose the first capacitance contains a reference charge with a positive or a negative polarity. First, the voltage on the first point is switched so that the first capcitance is charged from said first point and subsequently so that the first capcitance discharges towards the first point to its reference charge, which corresponds to said threshold level, in such a way that the net charge transfer from the first capacitance to the first point is equal to the positive or negative signal charge and the charge on the first capacitance is restored to a reference level.
摘要翻译：一种方法和装置，其中正和负信号电荷可以经由表现出阈值电平的晶体管电路从第一电容转移到第一点。为此，第一电容包含具有正极性或负极性的参考电荷。首先，切换第一点上的电压，使得第一电容从所述第一点充电并且随后使得第一电容朝向第一点放电至相应于所述阈值电平的参考电荷，使得从第一电容到第一点的净电荷转移等于正或负信号电荷，并且将第一电容上的电荷恢复到参考电平。

4. 发明授权

US4692737A Encoding device 失效
标题翻译：编码设备
公开(公告)号：US4692737A
公开(公告)日：1987-09-08
申请号：US920490
申请日：1986-10-17
申请人： Eduard F. Stikvoort , Arthur H. M. van Roermund , Peter J. A. Naus
发明人： Eduard F. Stikvoort , Arthur H. M. van Roermund , Peter J. A. Naus
IPC分类号： H03M1/12 , H03M3/02 , H03M1/00
CPC分类号： H03M3/444 , H03M3/43 , H03M3/436 , H03M3/456
摘要： A time-discrete amplitude-continuous or a time-discrete amplitude-discrete signal is converted in to a 1-bit encoded signal by means of a quantizer, the quantization-error signal being fed back via a loop filter. The transfer function of the loop filter is given by H(Z)=1-(Z-b).sup.n /(Z-a).sup.n, where n.gtoreq.3, b.perspectiveto.1 and 0

5. 发明授权

US4518935A Band-rejection filter of the switched capacitor type 失效
标题翻译：开关电容器类型的阻带滤波器
公开(公告)号：US4518935A
公开(公告)日：1985-05-21
申请号：US535497
申请日：1983-09-26
申请人： Arthur H. M. van Roermund
发明人： Arthur H. M. van Roermund
IPC分类号： H03H19/00
CPC分类号： H03H19/004
摘要： Band-rejection filter of the switched capacitor type in which at least one unwanted frequency component present in an information signal must be suppressed. To that end this filter comprises and adding circuit 4 to which the information signal is applied via a switching device 3 and a feedback signal via a switching device 5. Both switching devices are controlled by a first control signal consisting of a sequence of control signal periods of a duration T.sub.s which are each divided into a tracking phase and into an interrupt phase. During the tracking phase the signal can pass uninterruptedly through the switching device, while during the interrupt phase signals are not allowed to pass. The output of adding circuit 4 is coupled inter alia via a switching device 8 to the input of a bandpass filter 9 whose passband at least coincides with the unwanted frequency component. The switching device 8 is controlled by a second control signal which is also formed by a sequence of control signal periods of a duration T.sub.s and which are each divided into a tracking and an interrupt phase.In order to realize an adequate suppression of the unwanted frequency component the instants at which the tracking phases in the first control signal and the tracking phases in the second control signal end are mutually phase-shifted over a fixed distance.
摘要翻译：必须抑制存在于信息信号中的至少一个不需要的频率分量的开关电容器类型的阻带滤波器。为此，该滤波器包括和加法电路4，信号信号经由开关装置3施加到该信号信号和经由开关装置5的反馈信号。两个开关装置由第一控制信号控制，第一控制信号由一系列控制信号周期持续时间Ts被分成跟踪阶段和中断阶段。在跟踪阶段，信号可以不间断地通过开关装置，而在中断阶段，信号不允许通过。加法电路4的输出特别通过开关器件8耦合到带通至少与不需要的频率分量重合的带通滤波器9的输入端。开关装置8由也由持续时间Ts的一系列控制信号周期形成的第二控制信号控制，每个控制信号周期被分成跟踪和中断阶段。为了实现对不需要的频率分量的适当抑制，第一控制信号中的跟踪相位和第二控制信号端的跟踪相位在固定距离上相互相移。

6. 发明授权

US4517655A Multiplier circuit for multiplying an information signal by a periodic signal 失效
标题翻译：乘数电路，用于将信息信号乘以周期信号
公开(公告)号：US4517655A
公开(公告)日：1985-05-14
申请号：US416737
申请日：1982-09-10
申请人： Theodoor A. C. M. Claasen , Albert J. Stienstra , Arthur H. M. van Roermund
发明人： Theodoor A. C. M. Claasen , Albert J. Stienstra , Arthur H. M. van Roermund
IPC分类号： H03C1/00 , G06G7/16 , G06G7/161 , H03C1/54 , H03D1/22 , H03D7/00 , H04H1/00 , H04H20/48
CPC分类号： H04H20/48 , H03D1/22
摘要： Multiplier circuit for multiplying an information signal x(t) by a periodic signal y(t) having frequency f.sub.o, more specifically for amplitude modulation purposes in a stereo decoder. The multiplier circuit comprises N switching circuits 21(k) wherein k=0, 1, . . . N-1 which are each connected to a clock pulse generator 221, 222 by means of a control channel 25(k) and are each connected to an input of an adder device 28 by means of a signal channel 26(k). In addition, each switching circuit 21(k) receives the information signal x(t). A series of clock pulses g(k;t) is applied to each control channel in such a manner that for the control channel having number k these clock pulses occur at the instants t.sub.o +k(T.sub.o /N)+iT.sub.o wherein t.sub.o represents a constant T.sub.o =1/f.sub.o and i=. . . , -2, -1, 0, 1, 2, . . . Each signal channel 26(k) comprises a weighting network 27(k) having a constant weighting factor W(k) defined by the relation W(k)=y(t.sub.o +k(T.sub.o /N)). Each control channel 25(k) (or each signal channel 26(k)) incorporates a pulse reshaping circuit 24(k), which converts a pulse applied thereto into a pulse having a width equal to .tau.=T.sub.o /M wherein M represents an integer, for example M=N-1.
摘要翻译：用于将信息信号x（t）乘以具有频率fo的周期性信号y（t）的乘法器电路，更具体地用于立体声解码器中的幅度调制目的。乘法器电路包括其中k = 0,1，...的N个开关电路21（k）。的。的。 N-1各自通过控制信道25（k）连接到时钟脉冲发生器221,222，并且通过信号通道26（k）分别连接到加法器装置28的输入。另外，各切换电路21（k）接收信息信号x（t）。一系列时钟脉冲g（k; t）以这样的方式施加到每个控制信道，即对于具有数k的控制信道，这些时钟脉冲在时刻为+ k（To / N）+ iTo的时刻出现，其中，常数To = 1 / fo和i =。的。的。，-2，-1,0,1,2，...。的。的。每个信号信道26（k）包括具有由关系W（k）= y（to + k（To / N））定义的恒定加权因子W（k）的加权网络27（k）。每个控制通道25（k）（或每个信号通道26（k））包括脉冲整形电路24（k），其将施加到其上的脉冲转换成具有等于tau = To / M的宽度的脉冲，其中M表示整数，例如M = N-1。

7. 发明授权

US4716375A Switched-capacitor multiplier circuit 失效
标题翻译：开关电容倍增电路
公开(公告)号：US4716375A
公开(公告)日：1987-12-29
申请号：US878940
申请日：1986-06-26
申请人： Arthur H. M. van Roermund
发明人： Arthur H. M. van Roermund
IPC分类号： H03L7/085 , G06G7/16 , H03D1/22 , H03H19/00 , H03D3/18 , H03K5/00 , H03K17/00
CPC分类号： H03D1/22
摘要： A switched-capacitor multiplier circuit for multiplying an information signal x(t) by a bipolar carrier signal d(t) consisting of a distributed multiplier circuit with which the bipolar carrier signal is normally associated. To reduce offset voltages in the output signal caused by the operational amplifiers used and caused as a result of clock feed-through, it is not the bipolar carrier signal itself, but a full-wave rectified version thereof that is associated with the distributed multiplier circuit. The output signal of the multiplier circuit is applied to an auxiliary multiplier circuit multiplying it by +1 or -1 dependent on the instantaneous polarity of the bipolar carrier signal d(t). The offset voltage is thereby transposed to a frequency which is at least equal to the fundamental frequency of the carrier signal so that, if desired, it can be suppressed with the aid of a suitably chosen low-pass filter without the desired signal being affected thereby.
摘要翻译：一种用于将信息信号x（t）乘以由双极载波信号正常相关联的分布式乘法器电路组成的双极载波信号d（t）的开关电容倍增器电路。为了减少由于由于时钟馈通而使用和引起的运算放大器引起的输出信号中的偏移电压，它不是双极载波信号本身，而是与分布式乘法器电路相关联的全波整流版本。乘法器电路的输出信号被施加到辅助乘法器电路，根据双极性载波信号d（t）的瞬时极性将其乘以+1或-1。因此，偏移电压被转置到至少等于载波信号的基频的频率，使得如果需要，可以借助于适当选择的低通滤波器来抑制，而不影响期望的信号。

8. 发明授权

US4616192A Phase-locked loop with switchable phase detector 失效
标题翻译：带可切换相位检测器的锁相环
公开(公告)号：US4616192A
公开(公告)日：1986-10-07
申请号：US722891
申请日：1985-04-12
申请人： Arthur H. M. van Roermund
发明人： Arthur H. M. van Roermund
IPC分类号： H03L7/085 , H03L7/091 , H03L7/16
CPC分类号： H03L7/085
摘要： A phase-locked loop has a phase detector and a clock pulse oscillator. The phase detector multiplies a received reference signal by a comparison signal. It is constituted by a plurality of signal channels 207 each receiving the reference signal and having a cascade arrangement of a switching circuit 208 and a weighting network 209. The switching circuit is controlled by one or more sequences of main control pulses supplied by a pulse distributor circuit receiving clock pulses. Each signal channel has a constant weighting factor. For the k.sup.th signal channel the weighting factor is equal to the signal sample n(t.sub.o +kT.sub.s) of a fundamental signal n(t) which has a fundamental frequency f.sub.o. T.sub.s is the reciprocal of the clock pulse frequency f.sub.s. For each sequence of main control pulses controlling the switching circuit in the k.sup.th signal channel, this signal channel produces a main signal z(k, t). The main signals supplied by all the signal channels are added together. To allow locking of the loop on frequencies which are an integral multiple p of the fundamental frequency, the clock pulse oscillator has a frequency f.sub.s which is an integral multiple N of the fundamental frequency. In addition, the pulse distributor circuit has an input for setting the parameter p and at least N distributor outputs to which the several clock pulses are applied. More specifically, the clock pulse having number n is applied to the distributor output having number np modulo N. The sequence of pulses thus occurring at these distributor outputs constitutes the sequence of main control pulses.
摘要翻译：锁相环具有相位检测器和时钟脉冲振荡器。相位检测器将接收的参考信号乘以比较信号。它由多个信号通道207构成，每个信号通道207各自接收参考信号并具有开关电路208和加权网络209的级联布置。开关电路由脉冲分配器提供的一个或多个主控脉冲序列控制电路接收时钟脉冲。每个信号通道具有恒定的加权因子。对于第k个信号信道，加权因子等于具有基本频率fo的基本信号n（t）的信号样本n（to + kTs）。 Ts是时钟脉冲频率fs的倒数。对于控制第k信号通道中的开关电路的主控脉冲的每个序列，该信号通道产生主信号z（k，t）。所有信号通道提供的主要信号加在一起。为了允许在基频的整数倍的频率上锁定环路，时钟脉冲振荡器具有作为基频的整数倍的频率fs。此外，脉冲分配器电路具有用于设置参数p和至少施加几个时钟脉冲的N个分配器输出的输入。更具体地，具有数n的时钟脉冲被施加到编号为np模N的分配器输出。因此在这些分配器输出处发生的脉冲序列构成主控脉冲序列。

9. 发明授权

US4616185A Multiplying circuit comprising switched-capacitor circuits 失效
标题翻译：包含开关电容电路的乘法电路
公开(公告)号：US4616185A
公开(公告)日：1986-10-07
申请号：US630510
申请日：1984-06-13
申请人： Arthur H. M. van Roermund
发明人： Arthur H. M. van Roermund
IPC分类号： G06G7/16 , H03D1/22 , H03H19/00 , H04H20/88 , H03B19/00 , H03C1/00
CPC分类号： H03D1/22 , H03H19/004
摘要： Multiplying circuit for multiplying a first signal x(t) by a periodic second signal y(t) and being particularly suitable for use as an amplitude demodulator in a stereo decoder or in a phase-locked loop. It comprises N signal channels 26(k) wherein k=0, 1, . . . n-1, each receiving the first signal x(t) and each producing a channel signal. Each signal channel is formed by, arranged in cascade, a switched-capacitor circuit 28(k;1), 28(k;2), 29(k), the circuit included in the signal channel being controlled by a train of control pulses g(k,i) which each have a finite duration and occur with a repetition period T.sub.o and at instants t.sub.o +k(T.sub.o /N)+iT.sub.o where i= . . . -2, -1, 0, 1, 2, 3, . . . , means 29(k), 31, 30 for multiplying the amplitude of the signal x(t) by a constant weighting factor W(k) which is equal to y(t.sub.o +k(T.sub.o /N), pulse-reshaping means 29(k), 30, 31 for converting a pulse applied thereto into a pulse having a predetermined duration. The channel signals thus obtained are added together in an adder device 30, 31 to form a sum signal. This sum signal is sampled in a sampling arrangement 34(1), 34(2), 35 at instants comprised within the interval between the end of a control pulse g(k,i) and the beginning of the subsequent control pulse g(k+1,i).
摘要翻译：乘法电路，用于将第一信号x（t）乘以周期性第二信号y（t），并且特别适合用作立体声解码器或锁相环路中的幅度解调器。它包括N个信号通道26（k），其中k = 0,1，...。。。 n-1，每个接收第一信号x（t），并且各自产生信道信号。每个信号通道由级联的开关电容电路28（k; 1），28（k，2），29（k）组成，信号通道中包含的电路由一串控制脉冲 g（k，i）各自具有有限的持续时间，并且以重复周期To发生，并且在时刻为+ k（To / N）+ iTo，其中i =。。。 -2，-1，0，1，2，3，...。。。，用于将信号x（t）的振幅乘以等于y（to + k（To / N））的恒定加权因子W（k）的装置29（k），31,30，脉冲整形装置29 （k），30,31，用于将施加到其上的脉冲转换为具有预定持续时间的脉冲，由此获得的信道信号在加法器装置30,31中相加以形成和信号，该和信号以采样在控制脉冲g（k，i）的结束与随后的控制脉冲g（k + 1，i）的开始之间的间隔内的时刻的装置34（1），34（2），35。

10. 发明授权

US4860354A Arrangement for decoding a stereo multiplex signal 失效
标题翻译：用于解码立体声多路复用信号的装置
公开(公告)号：US4860354A
公开(公告)日：1989-08-22
申请号：US126381
申请日：1987-11-30
申请人： Arthur H. M. van Roermund
发明人： Arthur H. M. van Roermund
IPC分类号： H04H20/88 , H03D1/22 , H03H19/00 , H04B1/16
CPC分类号： H03D1/2236 , H03H19/00 , H04B1/1646
摘要： Arrangement for decoding a stereo multiplex signal, having a baseband stero signal (L+R), a stereo difference signal (L-R) which is amplitude-modulated on a suppressed sub-carrier, and a pilot signal having a frequency located between the frequency bands of the two signals, the arrangement having an input for the stereo multiplex signal and left and right stereo signal outputs, the input being coupled both, via a pilot selection circuit, to a phase-locked loop for regenerating the sub-carrier and to a multiplier circuit for multiplying at least the modulated stereo difference signal by the regenerated sub-carrier. In order to improve the stereo channel separation, the pilot selection circuit includes a bandpass filter of the switched capacitor type, a clock input of which is coupled to an output of an voltage-controlled oscillator incorporated in the loop. A mono-stereo control can be realized therein in a simple manner by varying the phase transfer of the switched capacitor bandpass filter at least at the pilot frequency in dependence upon a mono-stereo control signal.

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