专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07268569B2 Leakage current management 有权
标题翻译：漏电管理
公开(公告)号：US07268569B2
公开(公告)日：2007-09-11
申请号：US11027696
申请日：2004-12-28
申请人： Arman Vassighi , Ali Keshavarzi , Vivek K De
发明人： Arman Vassighi , Ali Keshavarzi , Vivek K De
IPC分类号： G01R31/02
CPC分类号： G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5006
摘要： A thermal feedback loop controls leakage current during burn-in of a circuit.
摘要翻译：热反馈回路控制电路老化期间的漏电流。

2. 发明申请

US20060140041A1 Leakage current management 有权
标题翻译：漏电管理
公开(公告)号：US20060140041A1
公开(公告)日：2006-06-29
申请号：US11027696
申请日：2004-12-28
申请人： Arman Vassighi , Ali Keshavarzi , Vivek De
发明人： Arman Vassighi , Ali Keshavarzi , Vivek De
IPC分类号： G11C8/00
CPC分类号： G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5006
摘要： A thermal feedback loop controls leakage current during burn-in of a circuit.
摘要翻译：热反馈回路控制电路老化期间的漏电流。

3. 发明授权

US07102358B2 Overvoltage detection apparatus, method, and system 有权
标题翻译：过电压检测装置，方法和系统
公开(公告)号：US07102358B2
公开(公告)日：2006-09-05
申请号：US10880337
申请日：2004-06-29
申请人： Ali Keshavarzi , Fabrice Paillet , Muhammad M Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H Tang , Mohsen Alavi , Vivek K De
发明人： Ali Keshavarzi , Fabrice Paillet , Muhammad M Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H Tang , Mohsen Alavi , Vivek K De
IPC分类号： G01R31/26
CPC分类号： G01R31/2621 , G01R19/16571
摘要： A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.
摘要翻译：由于过电压状态，晶体管可能具有劣化特性。可以感测劣化特性以确定晶体管先前已经经受过压状态。

4. 发明授权

US07072205B2 Floating-body DRAM with two-phase write 失效
标题翻译：具有两相写入的浮体DRAM
公开(公告)号：US07072205B2
公开(公告)日：2006-07-04
申请号：US10716755
申请日：2003-11-19
申请人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC分类号： G11C11/24 , G11C11/34
CPC分类号： G11C11/4094 , G11C11/404 , G11C11/4076 , G11C11/4085
摘要： A row of floating-body single transistor memory cells is written to in two phases.
摘要翻译：一行浮体单晶体管存储单元分两个阶段写入。

5. 发明授权

US07002842B2 Floating-body dynamic random access memory with purge line 失效
公开(公告)号：US07002842B2
公开(公告)日：2006-02-21
申请号：US10721184
申请日：2003-11-26
申请人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien Lu , Vivek K. De
发明人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien Lu , Vivek K. De
IPC分类号： G11C11/34
CPC分类号： H01L27/108 , G11C11/404
摘要： Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.

6. 发明授权

US07001811B2 Method for making memory cell without halo implant 失效
标题翻译：制造无光晕植入记忆细胞的方法
公开(公告)号：US07001811B2
公开(公告)日：2006-02-21
申请号：US10750566
申请日：2003-12-31
申请人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC分类号： H01L21/336
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/0207 , H01L27/0214 , H01L27/105 , H01L27/1052 , H01L27/108
摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.
摘要翻译：一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷第二种载体。根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结是不偏不倚的一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

7. 发明授权

US06593799B2 Circuit including forward body bias from supply voltage and ground nodes 有权
标题翻译：电路包括电源电压和接地节点的正向偏置
公开(公告)号：US06593799B2
公开(公告)日：2003-07-15
申请号：US09957996
申请日：2001-09-21
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： H03K301
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.
摘要翻译：本发明的一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。本发明的另一个实施例包括一个半导体电路，其包括提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型体的nFET晶体管，以使nFET晶体管的本体偏置转向。本发明的另一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。该电路还包括用于提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型主体的nFET晶体管，以使nFET晶体管的主体偏置转向。

8. 发明授权

US07355246B2 Memory cell without halo implant 有权
标题翻译：无光晕植入的记忆细胞
公开(公告)号：US07355246B2
公开(公告)日：2008-04-08
申请号：US11268430
申请日：2005-11-07
申请人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC分类号： H01L29/76
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/0207 , H01L27/0214 , H01L27/105 , H01L27/1052 , H01L27/108
摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.
摘要翻译：一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷第二种载体。根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结是不偏不倚的一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

9. 发明授权

US07321502B2 Non volatile data storage through dielectric breakdown 有权
标题翻译：非易失性数据存储通过介质击穿
公开(公告)号：US07321502B2
公开(公告)日：2008-01-22
申请号：US10956285
申请日：2004-09-30
申请人： Fabrice Paillet , Ali Keshavarzi , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H. Tang , Alavi Mohsen , Vivek K. De
发明人： Fabrice Paillet , Ali Keshavarzi , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H. Tang , Alavi Mohsen , Vivek K. De
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by interpreting behavior of the capacitor that is determined by the capacitor's resistance, where, the capacitor's resistance is a consequence of the inducing and the driving.
摘要翻译：描述了一种在驱动电流通过电容器的同时在电容器的电介质材料内感应电介质击穿的方法。电流特定于正在写入电容器的数据。该方法还涉及通过解释由电容器电阻确定的电容器的行为来读取数据，其中电容器的电阻是诱导和驱动的结果。

10. 发明授权

US07288752B2 CMOS radiation-measuring circuit with a variable threshold 有权
标题翻译：具有可变阈值的CMOS辐射测量电路
公开(公告)号：US07288752B2
公开(公告)日：2007-10-30
申请号：US10620829
申请日：2003-07-16
申请人： Ali Keshavarzi , Jaume A. Segura , Vivek K. De
发明人： Ali Keshavarzi , Jaume A. Segura , Vivek K. De
IPC分类号： G01J1/44 , H03K17/78
CPC分类号： G01T1/026 , H01L27/144
摘要： A radiation measuring technique includes adjusting a threshold level of a radiation sensor in a radiation-measuring circuit and obtaining an output signal based on radiation dose sensed by the radiation sensor.
摘要翻译：辐射测量技术包括调整辐射测量电路中的辐射传感器的阈值水平，并且基于由辐射传感器感测的辐射剂量获得输出信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式