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1. 发明申请

US20120001150A1 MEMORY CELL THAT EMPLOYS A SELECTIVELY FABRICATED CARBON NANO-TUBE REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME 有权
标题翻译：使用选择性的碳纳米管可逆电阻开关元件的记忆元件及其形成方法
公开(公告)号：US20120001150A1
公开(公告)日：2012-01-05
申请号：US13235409
申请日：2011-09-18
申请人： April D. Schricker , Wu-Yi Chien , Kun Hou , Raghuveer S. Makala , Jingyan Zhang , Yibo Nian
发明人： April D. Schricker , Wu-Yi Chien , Kun Hou , Raghuveer S. Makala , Jingyan Zhang , Yibo Nian
IPC分类号： H01L29/16 , H01L21/20 , B82Y40/00 , B82Y99/00
CPC分类号： B82Y10/00 , B82Y20/00 , G11C5/02 , G11C11/54 , G11C13/0014 , G11C13/025 , G11C2213/35 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/101 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1616
摘要： In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by selectively fabricating carbon nano-tube (“CNT”) material above the substrate, wherein the CNT material comprises a single CNT. Numerous other aspects are provided.
摘要翻译：在一些方面，提供一种制造存储单元的方法，其包括在基板上制造操纵元件，以及通过选择性地制造上述碳纳米管（“CNT”）材料制造耦合到转向元件的可逆电阻开关元件所述基板，其中所述CNT材料包括单个CNT。提供了许多其他方面。

2. 发明授权

US08878235B2 Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element and methods of forming the same 有权
标题翻译：采用选择性制造的碳纳米管可逆电阻切换元件的记忆单元及其形成方法
公开(公告)号：US08878235B2
公开(公告)日：2014-11-04
申请号：US13235409
申请日：2011-09-18
申请人： April D. Schricker , Wu-Yi Chien , Kun Hou , Raghuveer S. Makala , Jingyan Zhang , Yibo Nian
发明人： April D. Schricker , Wu-Yi Chien , Kun Hou , Raghuveer S. Makala , Jingyan Zhang , Yibo Nian
IPC分类号： H01L27/08 , H01L29/96 , H01L21/332 , B82Y10/00 , H01L45/00 , H01L27/10 , H01L27/24 , G11C13/00 , G11C5/02 , G11C11/54 , B82Y20/00 , G11C13/02
CPC分类号： B82Y10/00 , B82Y20/00 , G11C5/02 , G11C11/54 , G11C13/0014 , G11C13/025 , G11C2213/35 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/101 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1616
摘要： In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by selectively fabricating carbon nano-tube (“CNT”) material above the substrate, wherein the CNT material comprises a single CNT. Numerous other aspects are provided.
摘要翻译：在一些方面，提供一种制造存储单元的方法，其包括在基板上制造操纵元件，以及通过选择性地制造上述碳纳米管（“CNT”）材料制造耦合到转向元件的可逆电阻开关元件所述基板，其中所述CNT材料包括单个CNT。提供了许多其他方面。

3. 发明申请

US20130094278A1 Non-Volatile Memory Cell Containing an In-Cell Resistor 有权
标题翻译：含有单元电阻的非易失性存储单元
公开(公告)号：US20130094278A1
公开(公告)日：2013-04-18
申请号：US13552355
申请日：2012-07-18
申请人： Kun Hou , Yung-Tin Chen , Zhida Lan , Huiwen Xu
发明人： Kun Hou , Yung-Tin Chen , Zhida Lan , Huiwen Xu
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C17/16 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/51 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/146
摘要： A non-volatile memory cell includes a first electrode, a steering element, a metal oxide storage element located in series with the steering element, a dielectric resistor located in series with the steering element and the metal oxide storage element, and a second electrode.
摘要翻译：非易失性存储单元包括与转向元件串联设置的第一电极，操舵元件，金属氧化物存储元件，与转向元件和金属氧化物存储元件串联的介质电阻器和第二电极。

4. 发明授权

US08410582B2 3D polysilicon diode with low contact resistance and method for forming same 有权
标题翻译：具有低接触电阻的3D多晶硅二极管及其形成方法
公开(公告)号：US08410582B2
公开(公告)日：2013-04-02
申请号：US13479093
申请日：2012-05-23
申请人： Abhijit Bandyopadhyay , Kun Hou , Steven Maxwell
发明人： Abhijit Bandyopadhyay , Kun Hou , Steven Maxwell
IPC分类号： H01L29/66
CPC分类号： H01L29/868 , H01L27/2409 , H01L27/2481 , H01L29/165 , H01L29/452 , H01L29/456 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146
摘要： A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.
摘要翻译：半导体p-i-n二极管及其形成方法在此描述。在一个方面，在被掺杂为具有一个导电性（p +或n +）和与p-i-n二极管的电接触的区域之间形成SiGe区。 SiGe区域可以用于降低接触电阻，这可能增加正向偏置电流。掺杂区域延伸到SiGe区域的下方，使得其位于SiGe区域和二极管的本征区域之间。 p-i-n二极管可以由硅形成。 SiGe区域以下的掺杂区域可以用于保持反向偏置电流不增加，这是由于添加的SiGe区域的结果。在一个实施例中，SiGe被形成为使得存储器阵列中的向上指向的二极管的正向偏置电流基本上与向下指向的二极管的正向偏置电流匹配，其可以在这些二极管与 3D存储器阵列中的R / W材料。

5. 发明申请

US20120193756A1 DIODES WITH NATIVE OXIDE REGIONS FOR USE IN MEMORY ARRAYS AND METHODS OF FORMING THE SAME 有权
标题翻译：具有用于存储器阵列的内部氧化物区域的二极体及其形成方法
公开(公告)号：US20120193756A1
公开(公告)日：2012-08-02
申请号：US13020007
申请日：2011-02-02
申请人： Steven Maxwell , Abhijit Bandyopadhyay , Kun Hou , Er-Xuan Ping , Yung-Tin Chen , Li Xiao
发明人： Steven Maxwell , Abhijit Bandyopadhyay , Kun Hou , Er-Xuan Ping , Yung-Tin Chen , Li Xiao
IPC分类号： H01L29/861 , H01L21/36 , H01L29/92
CPC分类号： H01L27/1021 , H01L29/868 , Y10S438/90
摘要： In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided.
摘要翻译：在第一方面，提供一种垂直半导体二极管，其包括：（1）形成在基板上的第一半导体层; （2）形成在第一半导体层上方的第二半导体层; （3）形成在所述第一半导体层上方的第一自然氧化物层; 以及（4）形成在第一半导体层上的第三半导体层，第二半导体层和第一自然氧化物层，以形成包括第一自然氧化物层的垂直半导体二极管。提供了许多其他方面。

6. 发明申请

US20120091419A1 MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME 有权
标题翻译：具有与转向元件共享材料层的存储元件的存储单元及其形成方法
公开(公告)号：US20120091419A1
公开(公告)日：2012-04-19
申请号：US12905047
申请日：2010-10-14
申请人： Yung-Tin Chen , Chuanbin Pan , Andrei Mihnea , Steven Maxell , Kun Hou
发明人： Yung-Tin Chen , Chuanbin Pan , Andrei Mihnea , Steven Maxell , Kun Hou
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/146 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1616 , Y10S438/957
摘要： In some embodiments, a memory cell is provided that includes a storage element formed from an MIM stack including (1) a first conductive layer; (2) an RRS layer formed above the first conductive layer; and (3) a second conductive layer formed above the RRS layer, at least one of the first and second conductive layers comprising a first semiconductor material layer. The memory cell includes a steering element coupled to the storage element, the steering element formed from the first semiconductor material layer of the MIM stack and one or more additional material layers. Numerous other aspects are provided.
摘要翻译：在一些实施例中，提供了一种存储单元，其包括由MIM堆叠形成的存储元件，所述存储元件包括：（1）第一导电层; （2）形成在第一导电层上方的RRS层; 和（3）形成在RRS层之上的第二导电层，第一和第二导电层中的至少一个包括第一半导体材料层。存储单元包括耦合到存储元件的操纵元件，由MIM堆叠的第一半导体材料层形成的操纵元件和一个或多个附加材料层。提供了许多其他方面。

7. 发明申请

US20120091418A1 BIPOLAR STORAGE ELEMENTS FOR USE IN MEMORY CELLS AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：用于记忆细胞的双极存储元件及其形成方法
公开(公告)号：US20120091418A1
公开(公告)日：2012-04-19
申请号：US12904770
申请日：2010-10-14
申请人： Yung-Tin Chen , Franz Kreupl , Steven Maxwell , Kun Hou
发明人： Yung-Tin Chen , Franz Kreupl , Steven Maxwell , Kun Hou
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/149
摘要： In some embodiments, a memory cell is provided that includes (1) a bipolar storage element formed from a metal-insulator-metal (MIM) stack including (a) a first conductive layer; (b) a reversible resistivity switching (RRS) layer formed above the first conductive layer; (c) a metal/metal oxide layer stack formed above the first conductive layer; and (d) a second conductive layer formed above the RRS layer and the metal/metal oxide layer stack; and (2) a steering element coupled to the storage element. Numerous other aspects are provided.
摘要翻译：在一些实施例中，提供了一种存储单元，其包括：（1）由金属 - 绝缘体 - 金属（MIM）堆叠形成的双极存储元件，包括：（a）第一导电层; （b）形成在第一导电层之上的可逆电阻率切换（RRS）层; （c）形成在所述第一导电层上方的金属/金属氧化物层堆叠; 和（d）形成在RRS层和金属/金属氧化物层堆叠之上的第二导电层; 和（2）联接到存储元件的操纵元件。提供了许多其他方面。

8. 发明申请

US20120074367A1 COUNTER DOPING COMPENSATION METHODS TO IMPROVE DIODE PERFORMANCE 有权
标题翻译：计数器补偿方法提高二极管性能
公开(公告)号：US20120074367A1
公开(公告)日：2012-03-29
申请号：US12892633
申请日：2010-09-28
申请人： Xiying Costa , Abhijit Bandyopadhyay , Kun Hou , Brian Le , Yung-Tin Chen
发明人： Xiying Costa , Abhijit Bandyopadhyay , Kun Hou , Brian Le , Yung-Tin Chen
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1675
摘要： A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming a memory element coupled in series with the diode. Other aspects are also provided.
摘要翻译：提供一种形成存储单元的方法，所述方法包括形成二极管，该二极管包括具有第一导电类型的第一区域，对二极管进行反掺杂以将第一区域改变为第二导电类型，以及形成串联耦合的存储元件与二极管。还提供其他方面。

9. 发明申请

US20110062557A1 3D POLYSILICON DIODE WITH LOW CONTACT RESISTANCE AND METHOD FOR FORMING SAME 有权
标题翻译：具有低接触电阻的3D多晶硅二极管及其形成方法
公开(公告)号：US20110062557A1
公开(公告)日：2011-03-17
申请号：US12562079
申请日：2009-09-17
申请人： Abhijit Bandyopadhyay , Kun Hou , Steven Maxwell
发明人： Abhijit Bandyopadhyay , Kun Hou , Steven Maxwell
IPC分类号： H01L29/868 , H01L21/329
CPC分类号： H01L29/868 , H01L27/2409 , H01L27/2481 , H01L29/165 , H01L29/452 , H01L29/456 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146
摘要： A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.
摘要翻译：半导体p-i-n二极管及其形成方法在此描述。在一个方面，在被掺杂为具有一个导电性（p +或n +）和与p-i-n二极管的电接触的区域之间形成SiGe区。 SiGe区域可以用于降低接触电阻，这可能增加正向偏置电流。掺杂区域延伸到SiGe区域的下方，使得其位于SiGe区域和二极管的本征区域之间。 p-i-n二极管可以由硅形成。 SiGe区域以下的掺杂区域可以用于保持反向偏置电流不增加，这是由于添加的SiGe区域的结果。在一个实施例中，SiGe被形成为使得存储器阵列中的向上指向的二极管的正向偏置电流基本上与向下指向的二极管的正向偏置电流匹配，其可以在这些二极管与 3D存储器阵列中的R / W材料。

10. 发明授权

US08866124B2 Diodes with native oxide regions for use in memory arrays and methods of forming the same 有权
标题翻译：具有用于存储器阵列的自然氧化物区域的二极管及其形成方法
公开(公告)号：US08866124B2
公开(公告)日：2014-10-21
申请号：US13020007
申请日：2011-02-02
申请人： Steven Maxwell , Abhijit Bandyopadhyay , Kun Hou , Er-Xuan Ping , Yung-Tin Chen , Li Xiao
发明人： Steven Maxwell , Abhijit Bandyopadhyay , Kun Hou , Er-Xuan Ping , Yung-Tin Chen , Li Xiao
IPC分类号： H01L47/00 , H01L29/868 , H01L27/102
CPC分类号： H01L27/1021 , H01L29/868 , Y10S438/90
摘要： In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided.
摘要翻译：在第一方面，提供一种垂直半导体二极管，其包括：（1）形成在基板上的第一半导体层; （2）形成在第一半导体层上方的第二半导体层; （3）形成在所述第一半导体层上方的第一自然氧化物层; 以及（4）形成在第一半导体层上的第三半导体层，第二半导体层和第一自然氧化物层，以形成包括第一自然氧化物层的垂直半导体二极管。提供了许多其他方面。

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