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1. 发明专利

JP2008147644A Method of minimizing wet etch undercuts and carrying out pore-sealing to super-low k (k<2.5) dielectrics 有权
标题翻译：最小化水蚀蚀刻和超低密度K（K <2.5）电介质密封方法
公开(公告)号：JP2008147644A
公开(公告)日：2008-06-26
申请号：JP2007298307
申请日：2007-11-16
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： XU HUIWEN , SHEK MEI-YEE , XIA LI-QUN , AL-BAYATI AMIR , WITTY DEREK , M SAAD HICHEM
IPC分类号： H01L21/314 , C23C14/12 , H01L21/316 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a method of laminating a thin conformal pore-sealing surface layer on a low dielectric constant film on a substrate within a chamber. SOLUTION: A method includes a step of laminating a thin layer which includes silicon and carbon and may include oxygen and/or nitrogen by request on a film to process a patterned low dielectric constant film obtained after removing a photoresist from the film. The thin layer gives a hydrophobic surface including much carbon to the patterned low dielectric constant film 102. The thin layer also protects the low dielectric constant film from the subsequent wet cleaning process and penetration by a precursor of a layer subsequently laminated on the low dielectric constant film 102. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供在室内的基板上的低介电常数膜上层叠薄的共形孔密封表面层的方法。解决方案：一种方法包括层叠包含硅和碳的薄层，并且可以通过要求在薄膜上包括氧和/或氮以处理从膜中除去光致抗蚀剂之后获得的图案化的低介电常数膜的步骤。薄层给图案化的低介电常数膜102提供了包含大量碳的疏水表面。薄层还保护低介电常数膜免于随后的湿法清洗过程，并且通过随后层压在低介电常数上的层的前体电影102.版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2013102174A Method to obtain low k dielectric barrier with superior etching resistivity 审中-公开
标题翻译：获得具有超级蚀刻电阻率的低K电介质阻挡层的方法
公开(公告)号：JP2013102174A
公开(公告)日：2013-05-23
申请号：JP2012280516
申请日：2012-12-25
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： XU HUIWEN , LIU YIJUN JOHN , XIA LI-QUN , WITTY DEREK R , M SAAD HICHEM
IPC分类号： H01L21/312 , H01L21/768 , H01L23/532
CPC分类号： H01L21/3148 , C23C16/22 , C23C16/505 , H01L21/3121 , H01L21/3185
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a dielectric barrier with a low dielectric constant, improved etching resistivity, and excellent barrier performance.SOLUTION: There is provided a method for obtaining low K dielectric barrier with superior etching resistivity, which includes the steps of: flowing a precursor to a processing chamber, the precursor comprising a mixture of organic silicon compound and hydrocarbon compound, and the hydrocarbon compound comprising ethylene, propyne, or a combination thereof; generating low density plasma of the precursor in the processing chamber so as to form a silicon carbide based dielectric barrier film on a semiconductor substrate, the film having carbon-carbon bonds; securing the presence of at least a part of the carbon-carbon bonds contained in the precursor in the low density plasma and as well as in the dielectric barrier film; and eliminating from the dielectric barrier film carbon-carbon double bonds (C=C) and/or carbon-carbon triple bonds (C≡C) by introducing a controlled amount of nitrogen.
摘要翻译：要解决的问题：提供一种形成具有低介电常数，改善的蚀刻电阻率和优异的阻挡性能的介电阻挡层的方法。解决方案：提供了一种获得具有优良蚀刻电阻率的低K介电阻挡层的方法，其包括以下步骤：将前体流入处理室，前体包含有机硅化合物和烃化合物的混合物，以及包含乙烯，丙炔或其组合的烃化合物; 在处理室中产生前体的低密度等离子体，以在半导体衬底上形成碳化硅基电介质阻挡膜，该膜具有碳 - 碳键; 确保在低密度等离子体以及介电阻挡膜中存在前体中包含的至少一部分碳 - 碳键; 并通过引入受控量的氮而从电介质阻挡膜碳 - 碳双键（C = C）和/或碳 - 碳三键（C≡C）中消除。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2009170872A Method to obtain low k dielectric barrier with superior etching resistivity 审中-公开
标题翻译：获得具有超级蚀刻电阻率的低K电介质阻挡层的方法
公开(公告)号：JP2009170872A
公开(公告)日：2009-07-30
申请号：JP2008262106
申请日：2008-10-08
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： XU HUIWEN , LIU YIJUN JOHN , XIA LI-QUN , WITTY DEREK R , M SAAD HICHEM
IPC分类号： H01L21/312 , C23C16/42 , C23C16/505 , H01L21/318 , H01L21/768 , H01L23/522
CPC分类号： H01L21/3148 , C23C16/22 , C23C16/505 , H01L21/3121 , H01L21/3185
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a dielectric barrier with a low dielectric constant, improved etching resistivity, and excellent barrier characteristics.
SOLUTION: A method to process a semiconductor substrate includes a step to cause a precursor to flow to a processing chamber, wherein the precursor includes silicon-carbon bonding and carbon-carbon bonding, and a step to generate low density plasma of the precursor in the processing chamber to form a dielectric barrier film having the carbon-carbon bonding on the semiconductor substrate, wherein at least a portion of the carbon-carbon bonding in the precursor is preserved in the low density plasma and incorporated in the dielectric barrier film.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种形成具有低介电常数，改善的蚀刻电阻率和优异的阻挡特性的介电阻挡层的方法。解决方案：一种处理半导体衬底的方法包括使前体流到处理室的步骤，其中所述前体包括硅碳键和碳 - 碳键，以及产生低密度等离子体的步骤在所述处理室中形成具有在所述半导体衬底上的碳 - 碳键合的介电阻挡膜，其中所述前体中的所述碳 - 碳键合的至少一部分保留在所述低密度等离子体中并且并入所述介电阻挡膜中。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2009152544A Method of forming void in multilevel interconnection structure 有权
标题翻译：在多个互连结构中形成无效的方法
公开(公告)号：JP2009152544A
公开(公告)日：2009-07-09
申请号：JP2008263151
申请日：2008-10-09
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： XIA LI-QUN , XU HUIWEN , BALSEANU MIHAELA , SHEK MEIYEE MAGGIE LE , WITTY DEREK R , M SAAD HICHEM
IPC分类号： H01L21/768 , H01L21/306 , H01L21/314 , H01L23/522
CPC分类号： H01L21/76831 , C23C16/325 , H01L21/31144 , H01L21/3148 , H01L21/31633 , H01L21/76804 , H01L21/76807 , H01L21/7682 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76885 , H01L2221/1036
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a multilevel interconnection structure containing a void made of a material with a low dielectric constant without using a thermal process. SOLUTION: A trench is formed on a dielectric layer 105, and a conformal dielectric barrier film and a metal diffusion barrier film are deposited in the trench. The trench is filled with a conductive material to form a conductive line 109. A porous barrier 111 is formed on the dielectric layer and the conductive line. A photoresist 112 is generated, and an etchant is brought into contact with the dielectric layer through its hole 113 via the porous barrier. The dielectric layer is etched off to form the void 114. The conformal dielectric barrier film works as a barrier against a wet-etching chemical. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种在不使用热处理的情况下形成包含由具有低介电常数的材料制成的空隙的多层互连结构的方法。解决方案：在电介质层105上形成沟槽，并且在沟槽中沉积保形介电阻挡膜和金属扩散阻挡膜。沟槽填充有导电材料以形成导线109.多孔阻挡层111形成在电介质层和导电线上。产生光致抗蚀剂112，并通过多孔屏障使蚀刻剂通过其孔113与介电层接触。蚀刻掉电介质层以形成空隙114.保形介电阻挡膜用作抵抗湿蚀刻化学品的屏障。版权所有（C）2009，JPO＆INPIT

5. 发明申请

WO2006050482A2 HIGH-POWER DIELECTRIC SEASONING FOR STABLE WAFER-TO-WAFER THICKNESS UNIFORMITY OF DIELECTRIC CVD FILMS 审中-公开
标题翻译：高功率电介质用于稳定的波形到膜厚度的介电CVD膜的均匀性
公开(公告)号：WO2006050482A2
公开(公告)日：2006-05-11
申请号：PCT/US2005039899
申请日：2005-11-03
申请人： APPLIED MATERIALS INC , RAJAGOPALAN NAGARAJAN , XIA LI-QUN , BALSEANU MIHAELA , NOWAK THOMAS , SHAH RANJANA , XU HUIWEN , PETERSON CHAD , WITTY DEREK R , M SAAD HICHEM
发明人： RAJAGOPALAN NAGARAJAN , XIA LI-QUN , BALSEANU MIHAELA , NOWAK THOMAS , SHAH RANJANA , XU HUIWEN , PETERSON CHAD , WITTY DEREK R , M SAAD HICHEM
IPC分类号： C23C16/44 , H01L21/316
CPC分类号： C23C16/4404 , C23C16/4405 , H01L21/3121 , H01L21/31633
摘要： A method for seasoning a deposition chamber wherein the chamber components and walls are densely coated with a material that does not contain carbon prior to deposition of an organo-silicon material on a substrate. An optional carbon-containing layer may be deposited therebetween. A chamber cleaning method using low energy plasma and low pressure to remove residue from internal chamber surfaces is provided and may be combined with the seasoning process.
摘要翻译：一种用于调节沉积室的方法，其中在将有机硅材料沉积在基底上之前，室部件和壁被不含碳的材料密集地涂覆。可以在其间沉积任选的含碳层。提供了使用低能量等离子体和低压以从内部室表面除去残余物的室清洁方法，并且可以与调味过程组合。

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