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1. 发明专利

JP2009021584A High temperature etching method of high k material gate structure 审中-公开
标题翻译：高K材料门结构的高温蚀刻方法
公开(公告)号：JP2009021584A
公开(公告)日：2009-01-29
申请号：JP2008164459
申请日：2008-06-24
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： LIU WEI , MATSUSUE EIICHI , SHEN MEIHUA , DESHMUKH SHASHANK , KAWASE YOHEI , PHAN ANH-KIET QUANG , PALAGASHVILI DAVID , WILLWERTH MICHAEL D , SHIN JONG I , FINCH BARRETT
IPC分类号： H01L21/3065 , H01L21/28 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L21/3065 , H01L21/28282 , H01L21/31116 , H01L21/31122 , H01L21/32137
摘要： PROBLEM TO BE SOLVED: To provide a method of etching a high k material at a high temperature. SOLUTION: The method of etching a high k material on a substrate includes followings in one embodiment. A substrate comprising a high k material layer over itself is set in an etching chamber. Plasma is generated in the etching chamber from the etching gas mixture containing at least halogen-contained gas. While etching with the high k material layer under the presence of plasma, the surface temperature inside the etching chamber is kept at about 100°C or higher. The temperature of the substrate may be kept at 100°C-250°C while etching with the high k material layer under the presence of the plasma. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供在高温下蚀刻高k材料的方法。解决方案：在一个实施例中，蚀刻基板上的高k材料的方法包括以下。在蚀刻室中设置包括其自身上部的高k材料层的衬底。在至少含有卤素气体的蚀刻气体混合物的蚀刻室中产生等离子体。在等离子体存在下用高k材料层进行蚀刻时，蚀刻室内的表面温度保持在约100℃以上。在等离子体存在下，用高k材料层进行蚀刻时，基板的温度可以保持在100℃-250℃。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2014150268A Method of etching silicon-containing hard mask 有权
标题翻译：蚀刻含硅硬膜的方法
公开(公告)号：JP2014150268A
公开(公告)日：2014-08-21
申请号：JP2014053304
申请日：2014-03-17
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： YAN DU , SHEN MEIHUA , DESHMUKH SHASHANK C
IPC分类号： H01L21/3065 , H01J37/32 , H01L21/311 , H01L21/3213
CPC分类号： H01J37/32174 , H01J37/321 , H01L21/31116 , H01L21/32139
摘要： PROBLEM TO BE SOLVED: To vertically form an etching profile of a silicon-containing dielectric layer for use as a hard mask.SOLUTION: Plasma supply source gas including CFand CHF, a volumetric ratio of which is within the range of about 2:3 to about 3:1, more typically, about 1:1 to about 2:1, is employed and etching of a silicon-containing dielectric layer 110 is performed at a process chamber pressure within the range of about 4 mTorr to about 6 mTorr. Accordingly, there can be obtained: a selectivity for etching a silicon-containing dielectric layer relative to a photoresist 114 of 1.5:1 or more; and an etch profile sidewall angle within the range of 88°-92° between the etched silicon-containing dielectric layer and an underlying horizontal layer 108, in a semiconductor structure. There is also provided a smooth sidewall when used in combination with certain photoresists which are sensitive to 193 nm radiation.
摘要翻译：要解决的问题：垂直地形成用作硬掩模的含硅介电层的蚀刻轮廓。解决方案：包括CF和CHF的等离子体供应源气体，其体积比在约2:3至使用约3:1，更典型地为约1：1至约2:1，并且在约4mTorr至约6mTorr的范围内的处理室压力下进行含硅介电层110的蚀刻。因此，可以获得：相对于光致抗蚀剂114蚀刻含硅电介质层的选择性为1.5:1以上; 以及在半导体结构中在蚀刻的含硅介电层和下面的水平层108之间的88°-92°范围内的蚀刻轮廓侧壁角。当与某些对193纳米辐射敏感的光致抗蚀剂组合使用时，还提供了一个光滑的侧壁。

3. 发明专利

JP2011009761A Method of pattern etching silicon-containing hard mask 有权
标题翻译：图案蚀刻含硅硬质掩模的方法
公开(公告)号：JP2011009761A
公开(公告)日：2011-01-13
申请号：JP2010176396
申请日：2010-08-05
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： DU YAN , SHEN MEIHUA , DESHMUKH SHASHANK C
IPC分类号： H01L21/3065 , H01J37/32 , H01L21/311 , H01L21/3213
CPC分类号： H01J37/32174 , H01J37/321 , H01L21/31116 , H01L21/32139
摘要： PROBLEM TO BE SOLVED: To provide a method of pattern etching a layer of a silicon-containing dielectric substance.SOLUTION: This method uses a plasma supply source gas containing CFand CHFwithin the range of about 2:3 to about 3:1; more typically, about 1:1 to about 2:1. Etching is performed at a process chamber pressure within the range of about 4 mTorr to about 6 mTorr. The method provides a selectivity for etching a silicon-containing dielectric layer 110 relative to photoresist 114 of 1.5:1 or better. The method also provides an etching profile sidewall angle ranging from 88° to 92° between the etched silicon-containing dielectric layer 110 and an underlying horizontal layer 108 in the semi-conductor structure. The method provides a smooth sidewall when used in combination with a certain kind of photoresist which is sensitive to 193 nm radiant light.
摘要翻译：要解决的问题：提供一种图案蚀刻含硅介电物质层的方法。解决方案：该方法使用含有约2：3至约3：1范围内的CF和CHF的等离子体供应源气体; 更通常为约1：1至约2：1。在约4mTorr至约6mTorr的范围内的处理室压力下进行蚀刻。该方法提供了相对于光致抗蚀剂114蚀刻含硅介电层110的选择性为1.5:1或更好。该方法还提供在半导体结构中的蚀刻的含硅介电层110和下面的水平层108之间的从88°至92°的蚀刻轮廓侧壁角。当与193nm辐射光敏感的某种光致抗蚀剂组合使用时，该方法提供了平滑的侧壁。

4. 发明专利

JP2007235135A Etching method for forming anisotropic feature for high aspect ratio 审中-公开
标题翻译：用于形成高均匀度的各向异性特征的蚀刻方法
公开(公告)号：JP2007235135A
公开(公告)日：2007-09-13
申请号：JP2007045001
申请日：2007-02-26
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： LEUCKE UWE , SHEN MEIHUA , JIN GUANGXIANG , WANG XIKUN , LIU WEI , WILLIAMS SCOTT
IPC分类号： H01L21/3065 , H01L21/28 , H01L21/3213 , H01L29/423 , H01L29/49
CPC分类号： C23F4/00 , H01L21/3065 , H01L21/3086 , H01L21/31116 , H01L21/31122 , H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： PROBLEM TO BE SOLVED: To provide a forming method of an anisotropic feature for a high aspect ratio in an etching step.
SOLUTION: A disclosed method advantageously promotes the control of the profile and the size of the feature of a high aspect ratio through a side wall passivation management technique. In one embodiment, side wall passivation is managed by selectively forming an oxide passivation layer on the side wall and/or the bottom portion of an etching layer. In another embodiment, the passivation of the side wall is managed by maintaining a flat and uniform passivation layer on it by periodically removing an extra redeposition layer. It is made possible to gradually etch the feature of the high aspect ratio such that it is adapted to a depth desired for both high and low feature density regions on a substrate and the limit size of a vertical profile without generating a defect and/or the overetching of a lower layer using the flat and uniform passivation layer.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供在蚀刻步骤中用于高纵横比的各向异性特征的形成方法。解决方案：所公开的方法有利地通过侧壁钝化管理技术来促进高纵横比特征的轮廓和尺寸的控制。在一个实施例中，通过在蚀刻层的侧壁和/或底部上选择性地形成氧化物钝化层来管理侧壁钝化。在另一个实施例中，侧壁的钝化是通过周期性去除额外的再沉积层来维持平坦和均匀的钝化层来管理的。使得可以逐渐蚀刻高纵横比的特征，使得其适应于衬底上的高和低特征密度区域所需的深度以及垂直剖面的极限尺寸而不产生缺陷和/或使用平坦且均匀的钝化层对下层进行过蚀刻。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2008021975A Process for etching tungsten silicide on polysilicon particularly in flash memory 审中-公开
标题翻译：在闪存存储器中特别是多晶硅上浸渍二氧化硅的方法
公开(公告)号：JP2008021975A
公开(公告)日：2008-01-31
申请号：JP2007146380
申请日：2007-06-01
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： LEE KYEONG-TAE , CHOI JINHAN , JANG BI , DESHMUKH SHASHANK C , SHEN MEIHUA , LILL THORSTEN B , YU JAE BUM
IPC分类号： H01L21/3065 , H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/32136 , H01L21/28273 , H01L21/32137
摘要： PROBLEM TO BE SOLVED: To provide a method for performing plasma etching on tungsten silicide on polysilicon, the method being useful particularly for manufacturing flash memory requiring the long over etching time of micro loading and having both of a dense area and an isolation (iso) area.
SOLUTION: A bias power applied to a wafer is reduced in over etching. Main etching gas contains NF
3 and Cl
2 . Argon is added to prevent an undercut on a dense/iso contact. Oxygen and nitrogen oxidize any kind of exposed silicon to increase the selection ratio of etching and remove the distortions of an etching profile. SiCl
4 can be added to obtain an additional selection ratio.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种在多晶硅上对硅化钨执行等离子体蚀刻的方法，该方法特别用于制造需要长时间的微加载蚀刻时间并具有致密区域和隔离层的闪速存储器（iso）面积。解决方案：在过蚀刻中减少施加到晶片的偏置功率。主蚀刻气体含有NF 3 SB和SB SB 2。添加氩气以防止稠密/异种接触处的底切。氧和氮氧化任何种类的暴露的硅，以增加蚀刻的选择比率并消除蚀刻轮廓的变形。可以加入SiCl 4 以获得另外的选择比。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2007235136A Etching method for forming anisotropic feature for high aspect ratio 审中-公开
标题翻译：用于形成高均匀度的各向异性特征的蚀刻方法
公开(公告)号：JP2007235136A
公开(公告)日：2007-09-13
申请号：JP2007045100
申请日：2007-02-26
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： SHEN MEIHUA , LEUCKE UWE , JIN GUANGXIANG , WANG XIKUN , LIU WEI , WILLIAMS SCOTT
IPC分类号： H01L21/3065 , H01L21/28 , H01L21/283 , H01L21/3213 , H01L29/423 , H01L29/49
CPC分类号： H01L21/76802 , H01L21/32137 , H01L21/76814
摘要： PROBLEM TO BE SOLVED: To provide the forming method of an anisotropic feature for a high aspect ratio in an etching step.
SOLUTION: The method advantageously promotes the control of the profile and the size of the feature of a high aspect ratio through a side wall passivation management technique. A side wall passivation is managed by selectively forming an oxide passivation layer on the side wall and/or the bottom portion of an etching layer. The passivation of the side wall is managed by maintaining a flat and uniform passivation layer on it by periodically removing an extra redeposition layer. It is made possible to gradually etch the feature of the high aspect ratio such that it is adapted to a depth desired for both high and low feature density regions on a substrate and the limit size of a vertical profile without generating a defect and/or the overetching of a lower layer using the flat and uniform passivation layer.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供在蚀刻步骤中用于高纵横比的各向异性特征的形成方法。解决方案：该方法通过侧壁钝化管理技术有利地促进了高纵横比特征的轮廓和尺寸的控制。通过在蚀刻层的侧壁和/或底部选择性地形成氧化物钝化层来管理侧壁钝化。通过周期性去除额外的再沉积层，通过在其上维持平坦且均匀的钝化层来管理侧壁的钝化。使得可以逐渐蚀刻高纵横比的特征，使得其适应于衬底上的高和低特征密度区域所需的深度以及垂直剖面的极限尺寸而不产生缺陷和/或使用平坦且均匀的钝化层对下层进行过蚀刻。版权所有（C）2007，JPO＆INPIT

7. 发明公开

KR20070089062A ETCH METHODS TO FORM ANISOTROPIC FEATURES FOR HIGH ASPECT RATIO APPLICATIONS 审中-公开
标题翻译： ETCH方法形成高度比例应用的各向异性特征
公开(公告)号：KR20070089062A
公开(公告)日：2007-08-30
申请号：KR20070018392
申请日：2007-02-23
申请人： APPLIED MATERIALS INC
发明人： LEUCKE UWE , SHEN MEIHUA , JIN GUANGXIANG , WANG XIKUN , LIU WEI , WILLIAMS SCOTT
IPC分类号： H01L21/3065
CPC分类号： C23F4/00 , H01L21/3065 , H01L21/3086 , H01L21/31116 , H01L21/31122 , H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： An etching method for forming anisotropic features for high aspect ratio applications is provided to control easily the profiles and CDs(Critical Dimensions) of the features through a sidewall passivation managing member. A substrate is loaded in an etching chamber, wherein the substrate has a predetermined layer structure(202). The predetermined layer structure is etched through an opening portion of a mask layer in order to define a first portion of a feature by using a first gas compound(204). A re-deposition layer is formed while a second etching process is performed on the resultant structure by using a second gas compound. The opening portion is removed from the resultant structure by performing an in-situ etching process on the re-deposition layer. The predetermined layer is etched through the opening removed portion.
摘要翻译：提供了用于形成用于高纵横比应用的各向异性特征的蚀刻方法，以便通过侧壁钝化管理部件容易地控制特征的轮廓和CD（临界尺寸）。衬底被装载在蚀刻室中，其中衬底具有预定的层结构（202）。通过掩模层的开口部分蚀刻预定层结构，以便通过使用第一气体化合物（204）来限定特征的第一部分。在通过使用第二气体化合物对所得结构进行第二蚀刻处理时，形成再沉积层。通过对再沉积层进行原位蚀刻工艺，从所得结构中除去开口部分。通过开口移除部分蚀刻预定层。

8. 发明专利

SG144077A1 METHODS FOR RECESS ETCHING 未知
公开(公告)号：SG144077A1
公开(公告)日：2008-07-29
申请号：SG2007186455
申请日：2007-12-13
申请人： APPLIED MATERIALS INC
发明人： SHEN MEIHUA , CHEN RONG , WILLIAMS SCOTT
摘要： METHODS FOR RECESS ETCHING Methods for recess etching are provided herein that advantageously improve lateral to vertical etch ratio requirements, thereby enabling deeper recess etching while maintaining relatively shallow vertical etch depths. Such enhanced lateral etch methods advantageously provide benefits for numerous applications where lateral to vertical etch depth ratios are constrained or where recesses or cavities are desired to be formed. In some embodiments, a method of recess etching includes providing a substrate having a structure formed thereon; forming a recess in the substrate at least partially beneath the structure using a first etch process; forming a selective passivation layer on the substrate; and extending the recess in the substrate using a second etch process. The selective passivation layer is generally formed on regions of the substrate adjacent to the structure but generally not within the recess. The first and second etch processes may be the same or different.

9. 发明专利

DE10304851A1 未知
公开(公告)号：DE10304851A1
公开(公告)日：2003-08-21
申请号：DE10304851
申请日：2003-02-06
申请人： APPLIED MATERIALS INC
发明人： SHEN MEIHUA , DU YAN , GANI NICOLAS , YAUW ORANNA , OLUSEYI HAKEEM M
IPC分类号： H01L21/28 , H01L21/3213 , H01L29/49 , H01L21/336
摘要： Methods for etching electrodes formed directly on gate dielectrics are provided. In one aspect, an etch process is provided which includes a main etch step, a soft landing step, and an over etch step. In another aspect, a method is described which includes performing a main etch having good etch rate uniformity and good profile uniformity, performing a soft landing step in which a metal/metal barrier interface can be determined, and performing an over etch step to selectively remove the metal barrier without negatively affecting the dielectric. In another aspect, a method is provided which includes a first non-selective etch chemistry for bulk removal of electrode material, a second intermediate selective etch chemistry with end point capability, and then a selective etch chemistry to stop on the gate dielectric.

10. 发明专利

SG192540A1 WORKPIECE SUPPORT FOR A PLASMA REACTOR WITH CONTROLLED APPORTIONMENT OF RF POWER TO A PROCESS KIT RING 未知
公开(公告)号：SG192540A1
公开(公告)日：2013-08-30
申请号：SG2013055421
申请日：2009-07-13
申请人： APPLIED MATERIALS INC
发明人： COLLINS KENNETH S , BUCHBERGER DOUGLAS A JR , RAMASWAMY KARTIK , RAUF SHAHID , HANAWA HIROJI , SUN JENNIFER Y , NGUYEN ANDREW , LILL THORSTEN B , SHEN MEIHUA
摘要： In an electrostatic chuck, RF bias power is separately applied to a workpiece and to a process kit collar surrounding the workpiece. At least one variable impedance element governed by a system controller adjusts the apportionment of RF bias power between the workpiece and the process kit collar, allowing dynamic adjustment of the plasma sheath electric field at the extreme edge of the workpiece, for optimum electric field uniformity under varying plasma conditions, for example.FIGURE lA

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