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1. 发明专利

JP2008124460A Plasma for resist removal and facet control of feature under resist 有权
标题翻译：等离子体除锈和表面控制功能
公开(公告)号：JP2008124460A
公开(公告)日：2008-05-29
申请号：JP2007281585
申请日：2007-10-30
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： ZHOU YIFENG , LI SIYI , LEUNG TERRY , ARMACOST MICHAEL D
IPC分类号： H01L21/3065 , H01L21/027
CPC分类号： H01L21/31138 , G03F7/427 , H01J37/32706 , H01L21/76807
摘要： PROBLEM TO BE SOLVED: To process a substrate comprising a resist layer overlying a dielectric feature, in a substrate processing chamber comprising an antenna, and first and second process electrodes. SOLUTION: A process gas comprising CO 2 is introduced into the chamber. The process gas is energized to form a plasma by applying a source voltage to the antenna, and by applying to the electrodes, a first bias voltage having a first frequency of at least about 10 MHz and a second bias voltage having a second frequency of less than about 4 MHz. The ratio of the power level of the first bias voltage to the second bias voltage is so set that an edge facet height of the dielectric feature under the resist is at least about 10% of the height of the dielectric feature. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：在包括天线的基板处理室以及第一和第二处理电极中处理包括覆盖电介质特征的抗蚀剂层的基板。解决方案：将包含CO 2 的工艺气体引入室中。通过向天线施加源电压并且通过向电极施加具有至少约10MHz的第一频率的第一偏置电压和具有第二频率较小的第二偏置电压来对工艺气体进行通电以形成等离子体大约4 MHz。第一偏置电压的功率电平与第二偏置电压的比率被设定为使得抗蚀剂下方的电介质特征的边缘面高度至少为电介质特征的高度的约10％。版权所有（C）2008，JPO＆INPIT

2. 发明申请

WO2004038792A3 BARC SHAPING FOR IMPROVED FABRICATION OF DUAL DAMASCENE INTEGRATED CIRCUIT FEATURES 审中-公开
标题翻译：用于改进双组分集成电路特性的BARC形式
公开(公告)号：WO2004038792A3
公开(公告)日：2004-06-10
申请号：PCT/US0331824
申请日：2003-10-09
申请人： APPLIED MATERIALS INC
发明人： HSIEH CHANG-LIN , ZHANG QIQUN , YUAN JIE , LEUNG TERRY , HALIM SILVIA
IPC分类号： H01L21/768
CPC分类号： H01L21/76808
摘要： Method, materials and structures are described for the fabrication of dual damascene features in integrated circuits. In via-first dual damascene fabrication, a bottom-antireflective-coating ("BARC") is commonly deposited into the via and field regions surrounding the via, 107. Subsequent trench etch with conventional etching chemistries typically results in isolated regions of BARC, 107a, surrounded by "fencing" material, 108, at the bottom of the via. Such fencing hinders conformal coating with barrier/adhesion layers and can reduce device yield. The present invention relates to the formation of a BARCplug, 107, partially filling the via and having a convex upper surface, 400, prior to etching the trench. Such a BARC structure is shown to lead to etching without the formation of fencing and a clean dual damascene structure for subsequent coating. A directional anisotropic etching of BARC, and more particularly, an ammonia plasma etch, is one convenient method of removing BARC and forming the desired convex upper surface.
摘要翻译：描述了用于在集成电路中制造双镶嵌特征的方法，材料和结构。在通孔第一双镶嵌制造中，底部抗反射涂层（“BARC”）通常沉积在通孔107周围的通孔和场区域中。随后的常规蚀刻化学处理的沟槽蚀刻通常导致BARC 107a的隔离区域被围栏的“围栏”材料，108，在通道的底部。这种栅栏阻碍了具有阻挡层/粘合层的共形涂层并且可以降低器件产量。本发明涉及在蚀刻沟槽之前，形成部分地填充通孔并具有凸起的上表面400的BARC插头107。显示出这样一种BARC结构导致蚀刻而不形成栅栏和用于随后涂覆的清洁的双镶嵌结构。 BARC的定向各向异性蚀刻，更具体地说是氨等离子体蚀刻，是去除BARC并形成所需的凸上表面的一种方便的方法。

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