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1. 发明专利

JP2008182199A Multi-step dep-etch-dep (deposition-etching-deposition) high-density plasma chemical vapor deposition process for filling dielectric gap 有权
标题翻译：多层DEP-ETCH-DEP（沉积蚀刻沉积）高密度等离子体化学气相沉积工艺，用于填充电介质
公开(公告)号：JP2008182199A
公开(公告)日：2008-08-07
申请号：JP2007317207
申请日：2007-12-07
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： HUA ZHONG QIANG , PURNAWAN RIONARD , BLOKING JASON THOMAS , WANG ANCHUAN , LEE YOUNG S , YIEH ELLIE Y
IPC分类号： H01L21/316 , H01L21/31
CPC分类号： C23C16/401 , C23C16/045 , H01L21/02164 , H01L21/02274 , H01L21/31111 , H01L21/3145 , H01L21/31612
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a dielectric material in a substrate gap, using a high-density plasma.
SOLUTION: The method may include a step to deposit a first portion of the dielectric material into the gap by the high-density plasma. This deposition may form a protruding structure that at least partially blocks the deposition of the dielectric material into the gap. The first portion of dielectric material is exposed to an etchant that contains reactive species from a mixture, including NH
3 and NF
3 . The etchant forms a solid reaction product by the protruding structure, and the solid reaction product may be removed from the substrate. A final portion of the dielectric material may be deposited in the gap by the high-density plasma.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供使用高密度等离子体在基板间隙中形成电介质材料的方法。解决方案：该方法可以包括通过高密度等离子体将电介质材料的第一部分沉积到间隙中的步骤。该沉积可以形成至少部分地阻挡介电材料沉积到间隙中的突出结构。介电材料的第一部分暴露于包含来自混合物的反应物质的蚀刻剂，包括NH 3 SB 3和NF 3 SB 3。蚀刻剂通过突出结构形成固体反应产物，并且固体反应产物可以从基底上除去。电介质材料的最终部分可以通过高密度等离子体沉积在间隙中。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2001267315A IN SITU DEPOSITION AND INTEGRATION OF SILICON NITRIDE IN HIGH DENSITY PLASM REACTOR 失效
公开(公告)号：JP2001267315A
公开(公告)日：2001-09-28
申请号：JP2000392852
申请日：2000-12-25
申请人： APPLIED MATERIALS INC
发明人： HUA ZHONG QIANG , KHAZENI KASRA
IPC分类号： H01L21/205 , C23C16/34 , C23C16/40 , C23C16/42 , C23C16/505 , C23C16/56 , H01L21/31 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a method including a step for depositing a silicon oxide layer on a substrate and a step for deposition a dielectric film on the substrate constituted of a step processing a dielectric layer with oxygen. SOLUTION: The layer of FSG which is deposited in HDP-CVD and whose fluorine content is 7% or above when it is compared in peak high ratio, is processed with oxygen plasma. Thus, a film is stabilized or the thin layer (

3. 发明专利

SG184019A1 METHODS FOR FORMING LOW MOISTURE DIELECTRIC FILMS 未知
公开(公告)号：SG184019A1
公开(公告)日：2012-10-30
申请号：SG2012067443
申请日：2011-03-07
申请人： APPLIED MATERIALS INC
发明人： HUA ZHONG QIANG , LUO LEI , HERNANDEZ MANUEL A , CAO ZHITAO , SAPRE KEDAR , BHATNAGAR AJAY
摘要： A method for forming a pre-metal dielectric (PMD) layer or an inter-metal dielectric (IMD) layer over a substrate includes placing the substrate in a chemical vapor deposition (CVD) process chamber and forming a first oxide layer over the substrate in the CVD process chamber. The first oxide layer is formed using a thermal CVD process at a temperature of about 450°C or less and a sub-atmospheric pressure. The method also includes forming a second oxide layer over the first oxide layer in the CVD process chamber. The second oxide layer is formed using a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of about 450°C or less and a sub-atmospheric pressure. The substrate remains in the CVD process chamber during formation of the first oxide layer and the second oxide layer.

4. 发明专利

SG11201811611WA PROCESSED WAFER AS TOP PLATE OF A WORKPIECE CARRIER IN SEMICONDUCTOR AND MECHANICAL PROCESSING 未知
公开(公告)号：SG11201811611WA
公开(公告)日：2019-02-27
申请号：SG11201811611W
申请日：2017-06-01
申请人： APPLIED MATERIALS INC
发明人： NEMANI SRINIVAS D , ROY SHAMBHU N , PISHARODY GAUTAM , BUCHBERGER JR , YIEH ELLIE Y , HUA ZHONG QIANG
IPC分类号： H01L21/683 , H01L21/02

5. 发明专利

SG143230A1 MULTI-STEP DEP-ETCH-DEP HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION PROCESSES FOR DIELECTRIC GAPFILLS 未知
公开(公告)号：SG143230A1
公开(公告)日：2008-06-27
申请号：SG2007183197
申请日：2007-12-04
申请人： APPLIED MATERIALS INC
发明人： HUA ZHONG QIANG , PURNAWAN RIONARD , BLOKING JASON THOMAS , WANG ANCHUAN , LEE YOUNG S , YIEH ELLIE Y
IPC分类号： C23C16/44 , C23C16/52 , H01L21/3065
摘要： MULTI-STEP DEP-ETCH-DEP HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION PROCESSES FOR DIELECTRIC GAPFILLS A method of forming a dielectric material in a substrate gap using a high-density plasma is described. The method may include depositing a first portion of the dielectric material into the gap with the high-density plasma. The deposition may form a protruding structure that at least partially blocks the deposition of the dielectric material into the gap. The first portion of dielectric material is exposed to an etchant that includes reactive species from a mixture that includes NH[err] and NF[err]. The etchant forms a solid reaction product with the protruding structure, and the solid reaction product may be removed from the substrate. A final portion of the dielectric material may be deposited in the gap with the high-density plasma.

6. 发明申请

WO2011112402A2 IMPROVING CONFORMALITY OF OXIDE LAYERS ALONG SIDEWALLS OF DEEP VIAS 审中-公开
标题翻译：改善深奥维思德侧壁氧化物层的一致性
公开(公告)号：WO2011112402A2
公开(公告)日：2011-09-15
申请号：PCT/US2011026834
申请日：2011-03-02
申请人： APPLIED MATERIALS INC , HUA ZHONG QIANG , HERNANDEZ MANUEL A , LUO LEI , SAPRE KEDAR
发明人： HUA ZHONG QIANG , HERNANDEZ MANUEL A , LUO LEI , SAPRE KEDAR
IPC分类号： H01L21/316
CPC分类号： H01L21/76898
摘要： A method for improving conformality of oxide layers along sidewalls of vias in semiconductor substrates includes forming a nitride layer over an upper surface of a semiconductor substrate and forming a via extending through the nitride layer and into the semiconductor substrate. The via may have a depth of at least about 50 µm from a top surface of the nitride layer and an opening of less than about 10 µm at the top surface of the nitride layer. The method also includes forming an oxide layer over the nitride layer and along sidewalls and bottom of the via. The oxide layer may be formed using a thermal chemical vapor deposition (CVD) process at a temperature of less than about 450°C, where a thickness of the oxide layer at the bottom of the via is at least about 50% of a thickness of the oxide layer at the top surface of the nitride layer.
摘要翻译：一种用于改善沿着半导体衬底中的通孔的侧壁的氧化物层的共形性的方法包括在半导体衬底的上表面上方形成氮化物层并且形成延伸穿过氮化物层并进入半导体衬底的通孔。通孔可以具有距离氮化物层的顶表面至少约50μm的深度以及在氮化物层的顶表面处小于约10μm的开口。该方法还包括在氮化物层上并沿着通孔的侧壁和底部形成氧化物层。可以使用热化学气相沉积（CVD）工艺在低于约450℃的温度下形成氧化物层，其中在通孔底部的氧化物层的厚度为至少约50％的厚度氧化层位于氮化层的顶部表面。

7. 发明申请

WO2010047953A3 A REMOTE PLASMA CLEAN PROCESS WITH CYCLED HIGH AND LOW PRESSURE CLEAN STEPS 审中-公开
标题翻译：具有循环高低压清洁步骤的远程等离子清洁工艺
公开(公告)号：WO2010047953A3
公开(公告)日：2010-06-17
申请号：PCT/US2009059878
申请日：2009-10-07
申请人： APPLIED MATERIALS INC , HUA ZHONG QIANG , KAMATH SANJAY , LEE YOUNG S , YIEH ELLIE Y , LE HIEN-MINH HUU , PATEL ANJANA M , GONDHALEKAR SUDHIR R
发明人： HUA ZHONG QIANG , KAMATH SANJAY , LEE YOUNG S , YIEH ELLIE Y , LE HIEN-MINH HUU , PATEL ANJANA M , GONDHALEKAR SUDHIR R
IPC分类号： H01L21/3065 , H01L21/205 , H01L21/302
CPC分类号： B08B7/0035 , C23C16/4405
摘要： A remote plasma process for removing unwanted deposition build-up from one or more interior surfaces of a substrate processing chamber after processing a substrate disposed in the substrate processing chamber. In one embodiment, the substrate is transferred out of the substrate processing chamber and a flow of a fluorine-containing etchant gas is introduced into a remote plasma source where reactive species are formed. A continuous flow of the reactive species from the remote plasmas source to the substrate processing chamber is generated while a cycle of high and low pressure clean steps is repeated. During the high pressure clean step, reactive species are flown into the substrate processing chamber while pressure within the substrate processing chamber is maintained between 4-15 Torr. During the low pressure clean step, reactive species are flown into the substrate processing chamber while reducing the pressure of the substrate processing chamber by at least 50 percent of a high pressure reached in the high pressure clean step.
摘要翻译：一种远程等离子体处理，用于在处理设置在基板处理室中的基板之后从基板处理室的一个或多个内表面去除不想要的沉积物。在一个实施例中，将基板转移出基板处理室，并且将含氟蚀刻剂气体的流引入到其中形成反应性物质的远程等离子体源中。产生从远程等离子体源到基板处理室的反应物质的连续流动，同时重复高低压清洁步骤的循环。在高压清洁步骤期间，反应性物质流入基板处理室，同时基板处理室内的压力保持在4-15Torr之间。在低压清洁步骤期间，反应性物质流入基板处理室，同时将基板处理室的压力降低至高压清洁步骤达到的至少50％的高压。

8. 发明申请

WO2012021243A3 METHODS FOR FORMING LOW STRESS DIELECTRIC FILMS 审中-公开
标题翻译：形成低应力介电膜的方法
公开(公告)号：WO2012021243A3
公开(公告)日：2012-04-19
申请号：PCT/US2011043744
申请日：2011-07-12
申请人： APPLIED MATERIALS INC , HUA ZHONG QIANG , LUO LEI , HERNANDEZ MANUEL A , VENKATARAMAN SHANKAR
发明人： HUA ZHONG QIANG , LUO LEI , HERNANDEZ MANUEL A , VENKATARAMAN SHANKAR
IPC分类号： H01L21/316 , H01L21/205
CPC分类号： C23C16/513 , C23C16/401 , C23C16/44
摘要： A method for forming a multi-layer silicon oxide film on a substrate includes performing a deposition cycle that comprises depositing a silicon oxide layer using a thermal chemical vapor deposition (CVD) process and depositing a silicon oxide layer using a plasma enhanced chemical vapor deposition (PECVD) process. The deposition cycle is repeated a specified number of times to form the multi-layer silicon oxide film comprising a plurality of silicon oxide layers formed using the thermal CVD process and a plurality of silicon oxide layers formed using the PECVD process. Each silicon oxide layer formed using the thermal CVD process is adjacent to at least one silicon oxide layer formed using the PECVD process.
摘要翻译：一种用于在衬底上形成多层氧化硅膜的方法包括执行沉积循环，该沉积循环包括使用热化学气相沉积（CVD）工艺来沉积氧化硅层，并且使用等离子体增强化学气相沉积来沉积氧化硅层（ PECVD）过程。沉积循环重复指定的次数以形成包括使用热CVD工艺形成的多个氧化硅层和使用PECVD工艺形成的多个氧化硅层的多层氧化硅膜。使用热CVD工艺形成的每个氧化硅层与使用PECVD工艺形成的至少一个氧化硅层相邻。

9. 发明申请

WO2011112518A2 METHODS FOR FORMING LOW MOISTURE DIELECTRIC FILMS 审中-公开
标题翻译：形成低湿度电介质膜的方法
公开(公告)号：WO2011112518A2
公开(公告)日：2011-09-15
申请号：PCT/US2011027422
申请日：2011-03-07
申请人： APPLIED MATERIALS INC , HUA ZHONG QIANG , LUO LEI , HERNANDEZ MANUEL A , CAO ZHITAO , SAPRE KEDAR , BHATNAGAR AJAY
发明人： HUA ZHONG QIANG , LUO LEI , HERNANDEZ MANUEL A , CAO ZHITAO , SAPRE KEDAR , BHATNAGAR AJAY
IPC分类号： H01L21/205
CPC分类号： H01L21/02164 , C23C16/40 , C23C16/56 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02362
摘要： A method for forming a pre-metal dielectric (PMD) layer or an inter-metal dielectric (IMD) layer over a substrate includes placing the substrate in a chemical vapor deposition (CVD) process chamber and forming a first oxide layer over the substrate in the CVD process chamber. The first oxide layer is formed using a thermal CVD process at a temperature of about 450°C or less and a sub-atmospheric pressure. The method also includes forming a second oxide layer over the first oxide layer in the CVD process chamber. The second oxide layer is formed using a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of about 450°C or less and a sub-atmospheric pressure. The substrate remains in the CVD process chamber during formation of the first oxide layer and the second oxide layer.
摘要翻译：用于在衬底上形成预金属电介质（PMD）层或金属间电介质（IMD）层的方法包括将衬底放置在化学气相沉积（CVD）处理室中，并在衬底上形成第一氧化物层 CVD处理室。第一氧化物层使用热CVD工艺在约450℃或更低的温度和低于大气压的压力下形成。该方法还包括在CVD工艺室中的第一氧化物层上形成第二氧化物层。使用等离子体增强化学气相沉积（PECVD）工艺在约450℃或更低的温度和低于大气压的压力下形成第二氧化物层。在形成第一氧化物层和第二氧化物层期间衬底保留在CVD处理室中。

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