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1. 发明公开

EP1417532A1 METHODS FOR FORMING THERMO-OPTIC SWITCHES, ROUTERS AND ATTENUATORS 有权
标题翻译：方法用于制造光学热光交换机，路由器和衰减
公开(公告)号：EP1417532A1
公开(公告)日：2004-05-12
申请号：EP02795483.3
申请日：2002-07-16
申请人： Applied Materials, Inc.
发明人： KHAN, Anisul , KUMAR, Ajay
IPC分类号： G02F1/01
CPC分类号： G02F1/0147 , G02F1/011 , G02F1/313
摘要： Thermo-optic devices including a bottom cladding layer, a patterned core material and a top cladding layer, each having a different refractive index, can be made by depositing a heater material, such as tungsten or chromium, on the outside of the bottom and/or top cladding layer. Depending on the refractive index differences between the cladding layers and the core layers, the amount of heater material can also be varied. The heater material can surround the cladding layers, can be present on the sidewalls and top only, or the sidewalls alone, to provide sufficient heat to change the refractive index of the layers and thus the path of light passing through the device. These devices when built into the substrate can be connected to underlying devices and components formed on the same substrate for increased integration.

2. 发明公开

EP1240665A1 METAL MASK ETCHING OF SILICON 审中-公开
标题翻译：硅与口罩金属蚀刻
公开(公告)号：EP1240665A1
公开(公告)日：2002-09-18
申请号：EP00988213.5
申请日：2000-12-20
申请人： Applied Materials, Inc.
发明人： KUMAR, Ajay , KHAN, Anisul , LIU, Wei , CHAO, John , CHINN, Jeff
IPC分类号： H01L21/308
CPC分类号： H01L21/3081
摘要： The present disclosure provides a method for etching trenches, contact vias, or similar features. The method requires the use of a metal-comprising masking material in combination with a fluorine-comprising plasma etchant. The plasma feed gas includes at least one fluorine-containing compound such as nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), and sulfur hexafluoride (SF6). Oxygen (O2), or an oxygen-comprising compound, or hydrogen bromide (HBr), or a combination thereof may be added to the plasma feed gases.

3. 发明公开

EP1194952A2 FLUORINE BASED PLASMA ETCH METHOD FOR ANISOTROPIC ETCHING OF HIGH OPEN AREA SILICON STRUCTURES 审中-公开
标题翻译： ON典型大开口表面的硅衬底的各向异性蚀刻FLUOR基于PLASMAÄTZMETHODE
公开(公告)号：EP1194952A2
公开(公告)日：2002-04-10
申请号：EP00984407.7
申请日：2000-12-13
申请人： Applied Materials, Inc.
发明人： KUMAR, Ajay , KHAN, Ansul , PODLESNIK, Dragan, V. , CHINN, Jeffrey, D.
IPC分类号： H01L21/3065 , H01L21/311
CPC分类号： H01L21/31116 , H01L21/3065
摘要： A method for plasma etching substrates having high open area patterns is described. The method is useful in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used to etch strict profile control trenches with 89° +/-1° sidewalls on silicon substrates with high open area patterns such as patterns between about 50% and about 90%. The novel method plasma etches high open area substrates using a plasma formed from a gaseous mixture that includes an oxygen source gas, a fluorine source gas and a fluorocarbon source gas. In an alternative embodiment, the fluocarbon source gas is a passivation gas. In another alternative embodiment, the fluocarbon source gas consists essentially of a fluorocarbon having fluorine and carbon in a 2:1 ratio. In another particular embodiment, the oxygen source gas is O2, the fluorine source gas is SF6 and the fluorocarbon source gas is C4F8.

4. 发明公开

EP1330839A2 ETCHING OF HIGH ASPECT RATIO FEATURES IN A SUBSTRATE 审中-公开
标题翻译：结构研究ÄTUNG宽高比高基板的方法
公开(公告)号：EP1330839A2
公开(公告)日：2003-07-30
申请号：EP01987258.9
申请日：2001-11-01
申请人： Applied Materials, Inc.
发明人： KUMAR, Ajay , KHAN, Anisul , OUYE, Alan , WADENSWEILER, Ralph , KUMAR, Ananda , CHAFIN, Michael, G. , KHOLODENKO, Arnold , PODLESNIK, Dragan, V.
IPC分类号： H01L21/3065 , H01J37/32
CPC分类号： H01J37/32082 , H01J37/3266 , H01J2237/3347 , H01L21/31116
摘要： A substrate processing chamber (110) comprisea a gas supply (56) to provide a gas to the chamber, first and second electrodes (115, 105) that may be electrically biased to energize the gas, the second electrode (115) being adapted to be chargeable to a power density of at least about 10 watts/cm2, and the second electrode (115) comprising a receiving surface (147) to receive a substrate (10), and an exhaust (110) to exhaust the gas.

5. 发明申请

WO2015175267A1 DICING TAPE THERMAL MANAGEMENT BY WAFER FRAME SUPPORT RING COOLING DURING PLASMA DICING 审中-公开
标题翻译：通过水平框架支撑滚筒冷却的等温线热管理
公开(公告)号：WO2015175267A1
公开(公告)日：2015-11-19
申请号：PCT/US2015/029259
申请日：2015-05-05
申请人： APPLIED MATERIALS, INC.
发明人： LEI, Wei-Sheng , KUMAR, Prabhat , EATON, Brad , KUMAR, Ajay
IPC分类号： H01L21/301 , H01L21/78
CPC分类号： H01L21/82 , H01L21/3065 , H01L21/67 , H01L21/67069 , H01L21/67092 , H01L21/67109 , H01L21/67207 , H01L21/78
摘要： Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves introducing a substrate supported by a substrate carrier into a plasma etch chamber. The substrate has a patterned mask thereon covering integrated circuits and exposing streets of the substrate. The substrate carrier has a backside. The method also involves supporting at least a portion of the backside of the substrate carrier on a chuck of the plasma etch chamber. The method also involves cooling substantially all of the backside of the substrate carrier, the cooling involving cooling at least a first portion of the backside of the substrate carrier by the chuck. The method also involves plasma etching the substrate through the streets to singulate the integrated circuits while performing the cooling substantially all of the backside of the substrate carrier.
摘要翻译：对具有多个集成电路的各晶片的切割半导体晶片的方法和装置进行说明。在一个实例中，对具有多个集成电路的半导体晶片进行切割的方法包括将由衬底载体支撑的衬底引入等离子体蚀刻室。衬底上具有图案化掩模，覆盖集成电路并暴露衬底的街道。衬底载体具有背面。该方法还涉及将衬底载体的背侧的至少一部分支撑在等离子体蚀刻室的卡盘上。该方法还包括冷却基板载体的基本上所有背面，冷却涉及通过卡盘冷却基板载体的背面的至少第一部分。该方法还涉及通过街道等离子体蚀刻衬底以对集成电路进行单片化，同时基本上全部衬底载体的背面进行冷却。

6. 发明申请

WO2015153592A1 RESIDUE REMOVAL FROM SINGULATED DIE SIDEWALL 审中-公开
标题翻译：从平整的DIE小屋中移除残留物
公开(公告)号：WO2015153592A1
公开(公告)日：2015-10-08
申请号：PCT/US2015/023564
申请日：2015-03-31
申请人： APPLIED MATERIALS, INC.
发明人： LEI, Wei-Sheng , KUMAR, Prabhat , PAPANU, James S. , KUMAR, Ajay , EATON, Brad
IPC分类号： H01L21/301 , H01L21/76 , H01L21/78
CPC分类号： H01L21/02076 , H01L21/67092 , H01L21/67207
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the gaps in the mask to singulate the integrated circuits. The method also involves, subsequent to plasma etching the semiconductor wafer, removing etch residue from sidewalls of the singulated integrated circuits.
摘要翻译：对半导体晶片的切割方法，具有多个集成电路的各晶片进行说明。在一个示例中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。该方法还包括用激光划线工艺对掩模进行图案化以在掩模中提供间隙，在半导体晶片的间隙暴露集成电路之间的半导体晶片。该方法还包括通过掩模中的间隙等离子体蚀刻半导体晶片以对集成电路进行分离。该方法还涉及在等离子体蚀刻半导体晶片之后，从单个集成电路的侧壁去除蚀刻残留物。

7. 发明申请

WO2015134227A1 APPROACHES FOR CLEANING A WAFER DURING HYBRID LASER SCRIBING AND PLASMA ETCHING WAFER DICING PROCESSES 审中-公开
标题翻译：用于在混合激光切割和等离子体蚀刻波形处理过程中清洗波形的方法
公开(公告)号：WO2015134227A1
公开(公告)日：2015-09-11
申请号：PCT/US2015/017163
申请日：2015-02-23
申请人： APPLIED MATERIALS, INC.
发明人： HOLDEN, James Matthew , LEI, Wei-Sheng , PAPANU, James S. , KUMAR, Ajay
IPC分类号： H01L21/301 , H01L21/78
CPC分类号： H01L21/82 , H01J37/32009 , H01J37/3244 , H01L21/3081 , H01L21/428 , H01L21/467 , H01L21/6836 , H01L21/78 , H01L23/3192 , H01L23/544 , H01L24/13 , H01L2221/68327 , H01L2221/68377 , H01L2224/13022 , H01L2224/13082 , H01L2224/131 , H01L2224/27831 , H01L2224/94 , H01L2924/12041 , H01L2924/12042 , H01L2924/1436 , H01L2224/11 , H01L2924/014 , H01L2924/00
摘要： Approaches for cleaning a wafer during hybrid laser scribing and plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer having a front surface having a plurality of integrated circuits thereon involves forming an underfill material layer between and covering metal pillar/solder bump pairs of the integrated circuits. The method also involves forming a mask layer on the underfill material layer. The method also involves laser scribing mask layer and the underfill material layer to provide scribe lines exposing portions of the semiconductor wafer between the integrated circuits. The method also involves removing the mask layer. The method also involves, subsequent to removing the mask layer, plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, wherein the second insulating layer protects the integrated circuits during at least a portion of the plasma etching. The method also involves, subsequent to the plasma etching, thinning but not removing the underfill material layer to partially expose the metal pillar/solder bump pairs of the integrated circuits.
摘要翻译：描述了在混合式激光划线和等离子体蚀刻晶片切割工艺期间清洁晶片的方法。在一个例子中，对具有多个集成电路的前表面的半导体晶片进行切割的方法包括在集成电路的金属柱/焊料凸块对之间形成底部填充材料层。该方法还涉及在底部填充材料层上形成掩模层。该方法还包括激光划线掩模层和底部填充材料层，以提供在集成电路之间暴露半导体晶片的部分的划线。该方法还涉及去除掩模层。该方法还涉及在去除掩模层之后，通过划线等离子体蚀刻半导体晶片以对集成电路进行分离，其中第二绝缘层在等离子体蚀刻的至少一部分期间保护集成电路。该方法还包括在等离子体蚀刻之后，变薄而不去除底部填充材料层以部分地暴露集成电路的金属柱/焊料凸块对。

8. 发明申请

WO2015130575A1 HYBRID WAFER DICING APPROACH USING TEMPORALLY-CONTROLLED LASER SCRIBING PROCESS AND PLASMA ETCH 审中-公开
标题翻译：使用温度控制激光扫描过程和等离子体蚀刻的混合波形方法
公开(公告)号：WO2015130575A1
公开(公告)日：2015-09-03
申请号：PCT/US2015/016974
申请日：2015-02-20
申请人： APPLIED MATERIALS, INC.
发明人： PARK, Jungrae , LEI, Wei-Sheng , PAPANU, James S. , EATON, Brad , KUMAR, Ajay
IPC分类号： H01L21/301 , H01L21/78 , H01L21/76 , H01L21/268
CPC分类号： H01L21/78 , B23K26/0624 , B23K26/0661 , B23K26/18 , B23K26/364 , B23K2201/40 , B23K2203/166 , B23K2203/50 , B23K2203/56 , H01L21/02057 , H01L21/3065 , H01L21/30655 , H01L21/3086 , H01L21/31116 , H01L21/31138 , H01L21/32135
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a temporally-controlled laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The temporally-controlled laser scribing process involves scribing with a laser beam having a profile comprising a leading femto-second portion and a trailing lower-intensity, higher fluence portion. The method also involves plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.
摘要翻译：对半导体晶片的切割方法，具有多个集成电路的各晶片进行说明。在一个示例中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。该方法还包括用时间控制的激光划线工艺对掩模进行图案化，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。时间控制的激光划线方法包括用具有包括前导毫微微秒部分和尾随较低强度的较高注量部分的轮廓的激光束划线。该方法还包括通过图案化掩模中的间隙等离子体蚀刻半导体晶片以对集成电路进行分离。

9. 发明申请

WO2015116389A1 WAFER DICING USING HYBRID LASER SCRIBING AND PLASMA ETCH APPROACH WITH MASK PLASMA TREATMENT FOR IMPROVED MASK ETCH RESISTANCE 审中-公开
标题翻译：使用混合激光切割和等离子体蚀刻方法进行抛光加工，具有改进的掩模抗蚀性的掩模等离子体处理
公开(公告)号：WO2015116389A1
公开(公告)日：2015-08-06
申请号：PCT/US2015/011479
申请日：2015-01-14
申请人： APPLIED MATERIALS, INC.
发明人： LEI, Wei-Sheng , EATON, Brad , KUMAR, Ajay , PAPANU, James S. , PARK, Jungrae
IPC分类号： H01L21/301
CPC分类号： H01L21/78 , B23K26/361 , B23K2203/172 , B23K2203/50 , H01L21/0273 , H01L21/3065 , H01L21/30655 , H01L21/3081 , H01L21/3086 , H01L21/31058 , H01L21/31127 , H01L21/67207
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is exposed to a plasma treatment process to increase an etch resistance of the mask. The mask is patterned with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to exposing the mask to the plasma treatment process, the semiconductor wafer is plasma etched through the gaps in the mask to singulate the integrated circuits.
摘要翻译：对半导体晶片的切割方法，具有多个集成电路的各晶片进行说明。在一个例子中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。将掩模暴露于等离子体处理工艺以增加掩模的耐蚀刻性。用激光划线工艺对掩模进行图案化以在掩模中提供间隙，在半导体晶片的间隙暴露在集成电路之间。在将掩模暴露于等离子体处理工艺之后，通过掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

10. 发明申请

WO2015088791A1 METHOD AND CARRIER FOR DICING A WAFER 审中-公开
标题翻译：用于定位波形的方法和载体
公开(公告)号：WO2015088791A1
公开(公告)日：2015-06-18
申请号：PCT/US2014/067762
申请日：2014-11-26
申请人： APPLIED MATERIALS, INC.
发明人： HOLDEN, James M. , EATON, Brad , IYER, Aparna , KUMAR, Ajay
IPC分类号： H01L21/301
CPC分类号： H01L21/78 , B23Q3/18 , H01L21/3043 , H01L21/3065 , H01L21/308 , H01L21/67207 , H01L21/6836 , H01L22/26 , H01L2221/68327 , H01L2221/68377
摘要： Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a carrier for supporting a wafer or substrate in an etch process includes a frame having a perimeter surrounding an inner opening. The carrier also includes a tape coupled to the frame and disposed below the inner opening of the frame, the tape comprising an etch stop layer disposed above a support layer.
摘要翻译：描述了半导体晶片切割的方法和载体，每个晶片具有多个集成电路。在一个示例中，用于在蚀刻工艺中支撑晶片或衬底的载体包括具有围绕内部开口的周边的框架。载体还包括耦合到框架并且布置在框架的内部开口下方的带，该带包括设置在支撑层上方的蚀刻停止层。

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