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1. 发明申请

WO2022246009A1 SYSTEMS AND METHODS FOR BRIGHTNESS OR COLOR CONTROL IN FOLDABLE DISPLAYS 审中-公开
公开(公告)号：WO2022246009A1
公开(公告)日：2022-11-24
申请号：PCT/US2022/029924
申请日：2022-05-18
申请人： APPLE INC.
发明人： KIM, Hyunsoo , NHO, Hyunwoo , KIM, Hoon Sik , AGARWAL, Shatam , FARROKH BAROUGHI, Mahdi , HE, Xingfeng , KIM, ByoungSuk , ZHANG, Yifan , LIU, Yun , CHEN, Hao , DRZAIC, Paul S
IPC分类号： G09G5/10 , G09G3/00
摘要： The present disclosure relates to systems and methods to control brightness and color output in foldable displays (12). A foldable electronic display (12) may, when folded, include a first part (62) in a first plane and a second part (64) in a second plane different from the first plane. A brightness or color setting of the first part (62) may be controlled independently of a brightness or color setting of the second part (64). The first part (62) and the second part (64) may be foldable at a folding angle (270) with respect to one another. The processing circuitry may provide image data to the foldable electronic display (12) that varies based at least in part on the folding angle (270).

2. 发明申请

WO2014130316A1 METHOD AND DEVICE FOR SAVING POWER IN A DISPLAY PIPELINE BY POWERING DOWN IDLE COMPONENTS 审中-公开
标题翻译：用于通过向下移动的空闲部件供电来显示显示管道中的电源的方法和装置
公开(公告)号：WO2014130316A1
公开(公告)日：2014-08-28
申请号：PCT/US2014/015979
申请日：2014-02-12
申请人： APPLE INC.
发明人： HOLLAND, Peter , CHEN, Hao , KUO, Albert
IPC分类号： G06F1/32 , G06T3/40
CPC分类号： G06T1/60 , G06F1/3228 , G06F1/3265 , G06F1/3287 , G06T3/4007 , G09G5/363 , G09G5/391 , G09G5/395 , G09G5/399 , G09G2330/021 , G09G2340/0407 , G09G2340/045 , G09G2360/127 , Y02D10/153 , Y02D10/171 , Y02D50/20
摘要： Techniques are disclosed relating to power management within a display pipeline (200). The display buffer (114) receives image data (202) through a data transfer interconnect. A data transfer interconnect is powered down based on the display pipeline (200) operating in a scaling mode or in a non-scaling mode. The display buffer (114) transmits at least a portion of the image data to one or more components of the display pipeline (200), and in response to the transmitting, the data transfer interconnect is powered up. In some embodiments, the display buffer (114) includes a plurality of line buffers (310a-x), each configured to store a respective image source line (312). In such an embodiment, a display pipeline (200) configured to render images to be displayed includes the display buffer (114), and the powering down is performed in response to the received image data including two or more image source lines (312).
摘要翻译：公开了与显示管道（200）内的电源管理有关的技术。显示缓冲器（114）通过数据传输互连接收图像数据（202）。基于以缩放模式或非缩放模式操作的显示管线（200），数据传输互连被断电。显示缓冲器（114）将图像数据的至少一部分发送到显示管线（200）的一个或多个组件，并且响应于传送，数据传输互连通电。在一些实施例中，显示缓冲器（114）包括多个行缓冲器（310a-x），每个行缓冲器被配置为存储相应的图像源线（312）。在这种实施例中，被配置为显示图像的显示管线（200）包括显示缓冲器（114），并且响应于包括两个或多个图像源线（312）的接收到的图像数据执行掉电。

3. 发明申请

WO2014052543A1 EFFICIENT PROCESSING OF ACCESS REQUESTS FOR A SHARED RESOURCE 审中-公开
标题翻译：有效地处理共享资源的访问请求
公开(公告)号：WO2014052543A1
公开(公告)日：2014-04-03
申请号：PCT/US2013/061849
申请日：2013-09-26
申请人： APPLE INC.
发明人： HOLLAND, Peter F. , CHEN, Hao
IPC分类号： G06F13/16
CPC分类号： G06F13/1663
摘要： A system and method for efficiently processing access requests for a shared resource. A computing system includes a shared memory accessed by multiple requestors. Control logic determines two requestors seek to access a same data block within the shared memory. In response to the determination, a first requestor of the two requestors sends a read request to the shared memory on behalf of the two requestors. The second requestor of the two requestors is prevented from sending a read request. In response to detecting data is returned as a response to the read request generated by the first requestor, both the first requestor and the second requestor retrieve the data. In response to detecting a given requestor of the two requestors generates an indication that it is unable to continue retrieving the same response data, the two requestors return to generating separate, respective read requests.
摘要翻译：一种用于有效地处理共享资源的访问请求的系统和方法。计算系统包括由多个请求者访问的共享存储器。控制逻辑确定两个请求者寻求访问共享存储器内的相同数据块。响应于该确定，两个请求者的第一请求者代表两个请求者向共享存储器发送读请求。两个请求者的第二请求者被阻止发送读请求。响应于检测数据作为对由第一请求者产生的读取请求的响应而返回，第一请求者和第二请求者都检索数据。响应于检测到两个请求者的给定请求者产生不能继续检索相同响应数据的指示，两个请求者返回产生单独的相应读请求。

4. 发明申请

WO2013036477A1 DYNAMIC DATA STROBE DETECTION 审中-公开
标题翻译：动态数据结构检测
公开(公告)号：WO2013036477A1
公开(公告)日：2013-03-14
申请号：PCT/US2012/053656
申请日：2012-09-04
申请人： APPLE INC. , CHEN, Hao , NOTANI, Rakesh L. , BISWAS, Sukalpa
发明人： CHEN, Hao , NOTANI, Rakesh L. , BISWAS, Sukalpa
IPC分类号： G11C7/00
CPC分类号： G06F13/1689
摘要： Techniques are disclosed relating to determining when a data strobe signal is valid for capturing data. In one embodiment, an apparatus is disclosed that includes a memory interface circuit configured to determine an initial time value for capturing data from a memory based on a data strobe signal. In some embodiments, the memory interface circuit may determine this initial time value by reading a known value from memory. In one embodiment, the memory interface circuit further configured to determine an adjusted time value for capturing the data, where the memory interface circuit is configured to determine the adjusted time value by using the initial time value to sample the data strobe signal.
摘要翻译：公开了关于确定何时数据选通信号对于捕获数据有效的技术。在一个实施例中，公开了一种装置，其包括存储器接口电路，其被配置为基于数据选通信号来确定用于从存储器捕获数据的初始时间值。在一些实施例中，存储器接口电路可以通过从存储器读取已知值来确定该初始时间值。在一个实施例中，存储器接口电路还被配置为确定用于捕获数据的经调整的时间值，其中存储器接口电路被配置为通过使用初始时间值来对数据选通信号进行采样来确定调整的时间值。

5. 发明申请

WO2012071197A1 MECHANISM FOR AN EFFICIENT DLL TRAINING PROTOCOL DURING A FREQUENCY CHANGE 审中-公开
标题翻译：在频率变化期间有效的DLL训练协议的机制
公开(公告)号：WO2012071197A1
公开(公告)日：2012-05-31
申请号：PCT/US2011/060518
申请日：2011-11-14
申请人： APPLE INC. , MACHNICKI, Erik P. , CHEN, Hao , MANSINGH, Sanjay
发明人： MACHNICKI, Erik P. , CHEN, Hao , MANSINGH, Sanjay
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0814
摘要： An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit.
摘要翻译：在频率变化期间，有效的延迟锁定环（DLL）训练协议包括具有包含主DLL和从属DLL的存储器物理层（PHY）单元的集成电路。主DLL可以将第一参考时钟延迟一定量，并提供对应于延迟量的参考延迟值。从属DLL可以基于接收的配置延迟值将第二参考时钟延迟第二量。接口单元可以基于参考延迟值生成配置延迟值。功率管理单元可以提供第二参考时钟的频率正在改变的指示。响应于接收到指示，接口单元可以使用预定的缩放值来生成对应于新频率的新的配置延迟值，并向存储器PHY单元提供新的配置延迟值。

6. 发明申请

WO2012036905A1 MULTI-PORTED MEMORY CONTROLLER WITH PORTS ASSOCIATED WITH TRAFFIC CLASSES 审中-公开
标题翻译：多通道存储器控制器，带有与业务类相关的端口
公开(公告)号：WO2012036905A1
公开(公告)日：2012-03-22
申请号：PCT/US2011/049940
申请日：2011-08-31
申请人： APPLE INC. , BISWAS, Sukalpa , CHEN, Hao , WADHAWAN, Ruchi
发明人： BISWAS, Sukalpa , CHEN, Hao , WADHAWAN, Ruchi
IPC分类号： G06F13/00
CPC分类号： G06F13/1642 , G06F13/1626
摘要： In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.
摘要翻译：在一个实施例中，存储器控制器包括多个端口。每个端口可能专用于不同类型的流量。在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。存储器控制器可以被配置为基于QoS参数在不同端口上接收的调度操作。在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。

7. 发明申请

WO2011153072A1 CRITICAL WORD FORWARDING WITH ADAPTIVE PREDICTION 审中-公开
标题翻译：具有适应性预测的关键词
公开(公告)号：WO2011153072A1
公开(公告)日：2011-12-08
申请号：PCT/US2011/038171
申请日：2011-05-26
申请人： APPLE INC. , LILLY, Brian P. , KASSOFF, Jason M. , CHEN, Hao
发明人： LILLY, Brian P. , KASSOFF, Jason M. , CHEN, Hao
IPC分类号： G06F13/16
CPC分类号： G06F13/1668 , G06F12/0862
摘要： In an embodiment, a system includes a memory controller, processors and corresponding caches. The system may include sources of uncertainty that prevent the precise scheduling of data forwarding for a load operation that misses in the processor caches. The memory controller may provide an early response that indicates that data should be provided in a subsequent clock cycle. An interface unit between the memory controller and the caches/processors may predict a delay from a currently-received early response to the corresponding data, and may speculatively prepare to forward the data assuming that it will be available as predicted. The interface unit may monitor the delays between the early response and the forwarding of the data, or at least the portion of the delay that may vary. Based on the measured delays, the interface unit may modify the subsequently predicted delays.
摘要翻译：在一个实施例中，系统包括存储器控制器，处理器和对应的高速缓存。该系统可以包括不确定性源，其阻止针对处理器高速缓存中丢失的加载操作的数据转发的精确调度。存储器控制器可以提供指示在随后的时钟周期中应该提供数据的早期响应。存储器控制器和高速缓存/处理器之间的接口单元可以预测从当前接收的早期响应到相应数据的延迟，并且可以推测地准备转发数据，假设它将如预期的那样可用。接口单元可以监视早期响应和数据转发之间的延迟，或至少可能变化的部分延迟。基于测量的延迟，接口单元可以修改随后预测的延迟。

8. 发明公开

EP2539824A1 CRITICAL WORD FORWARDING WITH ADAPTIVE PREDICTION 审中-公开
标题翻译：美国麻省理工学院适应症VERZÖGERUNGSVORHERSAGE
公开(公告)号：EP2539824A1
公开(公告)日：2013-01-02
申请号：EP11743162.7
申请日：2011-05-26
申请人： Apple Inc.
发明人： LILLY, Brian P. , KASSOFF, Jason M. , CHEN, Hao
IPC分类号： G06F13/16
CPC分类号： G06F13/1668 , G06F12/0862
摘要： In an embodiment, a system includes a memory controller, processors and corresponding caches. The system may include sources of uncertainty that prevent the precise scheduling of data forwarding for a load operation that misses in the processor caches. The memory controller may provide an early response that indicates that data should be provided in a subsequent clock cycle. An interface unit between the memory controller and the caches/processors may predict a delay from a currently-received early response to the corresponding data, and may speculatively prepare to forward the data assuming that it will be available as predicted. The interface unit may monitor the delays between the early response and the forwarding of the data, or at least the portion of the delay that may vary. Based on the measured delays, the interface unit may modify the subsequently predicted delays.
摘要翻译：在一个实施例中，系统包括存储器控制器，处理器和对应的高速缓存。该系统可以包括不确定性源，其阻止针对处理器高速缓存中丢失的加载操作的数据转发的精确调度。存储器控制器可以提供指示在随后的时钟周期中应该提供数据的早期响应。存储器控制器和高速缓存/处理器之间的接口单元可以预测从当前接收的早期响应到相应数据的延迟，并且可以推测地准备转发数据，假设它将如预期的那样可用。接口单元可以监视早期响应和数据转发之间的延迟，或至少可能变化的延迟部分。基于测量的延迟，接口单元可以修改随后预测的延迟。

9. 发明公开

EP4214922A1 BOUNDARY SMOOTHING IN A DISPLAY 审中-实审
公开(公告)号：EP4214922A1
公开(公告)日：2023-07-26
申请号：EP21758274.1
申请日：2021-08-02
申请人： Apple Inc.
发明人： HE, Juan , QI, Jun , CHEN, Hao , HUANG, Yi-Pai , ZHANG, Sheng , HUANG, Yi , KIM, ByoungSuk , CHOU, Ping-Yen , MA, Yue
IPC分类号： H04N13/305 , G09G3/20 , G02B30/27

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