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1. 发明申请

US20060249785A1 Power MOSFET device structure for high frequency applications 有权
标题翻译：功率MOSFET器件结构用于高频应用
公开(公告)号：US20060249785A1
公开(公告)日：2006-11-09
申请号：US11125506
申请日：2005-05-09
申请人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik Lui
发明人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik Lui
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66712 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41775 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/7802 , H01L29/7811 , H01L29/7827
摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.
摘要翻译：本发明公开了一种支撑在半导体上的新开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的所述半导体的第二表面附近的源极区域。开关装置还包括设置在第二表面顶部的用于控制源极到漏极电流的绝缘栅电极。开关装置还包括插入到绝缘栅电极中的源电极，用于基本上防止栅电极和绝缘栅电极下方的外延区之间的电场的耦合。源电极进一步覆盖并延伸在绝缘栅上，以覆盖半导体的第二表面上的区域以接触源区。半导体衬底还包括设置在漏极区以上且具有与漏极区不同的掺杂浓度的外延层。绝缘栅电极还包括用于使栅电极与源电极绝缘的绝缘层，其中绝缘层的厚度取决于垂直功率器件的Vgsmax等级。

2. 发明申请

US20080001219A1 Power MOS device 有权
公开(公告)号：US20080001219A1
公开(公告)日：2008-01-03
申请号：US11900603
申请日：2007-09-11
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.

3. 发明申请

US20120329225A1 POWER MOS DEVICE FABRICATION 有权
标题翻译：电源MOS器件制造
公开(公告)号：US20120329225A1
公开(公告)日：2012-12-27
申请号：US13604286
申请日：2012-09-05
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： Fabricating a semiconductor device includes forming a mask on a substrate having a top substrate surface; forming a gate trench in the substrate, through the mask; depositing gate material in the gate trench; removing the mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region; and disposing conductive material in the source body contact trench, on top of the plug.
摘要翻译：制造半导体器件包括在具有顶部衬底表面的衬底上形成掩模; 通过掩模在衬底中形成栅极沟槽; 在栅极沟槽中沉积栅极材料; 取下面罩离开门结构; 植入人体区域; 植入源区; 形成具有沟槽壁和沟槽底部的源体接触沟槽; 在源体接触沟槽中形成插塞，其中插头延伸到身体区域的底部下方; 并且在所述源体接触沟槽中，在所述插头的顶部上设置导电材料。

4. 发明申请

US20090224316A1 Power MOS device with conductive contact layer 有权
标题翻译：功率MOS器件具有导电接触层
公开(公告)号：US20090224316A1
公开(公告)日：2009-09-10
申请号：US12384172
申请日：2009-03-31
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/772
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device includes a drain, a body disposed over the drain, a source embedded in the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench extending through the source into the body, a conductive contact layer disposed along at least a portion of a source body contact trench sidewall and in contact with at least a portion of the source, and a trench filling material disposed in the source body contact trench and overlaying at least a portion of the conductive contact layer.
摘要翻译：半导体器件包括漏极，设置在漏极上的主体，嵌入在主体中的源极，通过源极和主体延伸到漏极中的栅极沟槽，设置在栅极沟槽中的栅极，源体接触沟槽延伸穿过源体进入体内，导电接触层沿着源体接触沟槽侧壁的至少一部分设置并与源的至少一部分接触，以及沟槽填充材料，其设置在源体接触沟槽中并覆盖在至少一部分导电接触层。

5. 发明申请

US20060180855A1 Power MOS device 有权
标题翻译：功率MOS器件
公开(公告)号：US20060180855A1
公开(公告)日：2006-08-17
申请号：US11056346
申请日：2005-02-11
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.
摘要翻译：半导体器件包括漏极，设置在漏极上的主体，具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中;延伸穿过源和主体的栅沟槽，漏极，设置在栅极沟槽中的栅极，具有沟槽壁的源体接触沟槽和沿着沟槽壁布置的抗穿孔植入物。制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成栅极沟槽，通过硬掩模，在栅极沟槽中沉积栅极材料，去除硬掩模以留下栅极形成具有沟槽壁并形成抗穿孔植入物的源体接触沟槽。

6. 发明授权

US07923774B2 Power MOS device with conductive contact layer 有权
标题翻译：功率MOS器件具有导电接触层
公开(公告)号：US07923774B2
公开(公告)日：2011-04-12
申请号：US12384172
申请日：2009-03-31
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device includes a drain, a body disposed over the drain, a source embedded in the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench extending through the source into the body, a conductive contact layer disposed along at least a portion of a source body contact trench sidewall and in contact with at least a portion of the source, and a trench filling material disposed in the source body contact trench and overlaying at least a portion of the conductive contact layer.
摘要翻译：半导体器件包括漏极，设置在漏极上的主体，嵌入在主体中的源极，通过源极和主体延伸到漏极中的栅极沟槽，设置在栅极沟槽中的栅极，源体接触沟槽延伸穿过源体进入体内，导电接触层沿着源体接触沟槽侧壁的至少一部分设置并与源的至少一部分接触，以及沟槽填充材料，其设置在源体接触沟槽中并覆盖在至少一部分导电接触层。

7. 发明授权

US07285822B2 Power MOS device 有权
标题翻译：功率MOS器件
公开(公告)号：US07285822B2
公开(公告)日：2007-10-23
申请号：US11056346
申请日：2005-02-11
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall.A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.
摘要翻译：半导体器件包括漏极，设置在漏极上的主体，具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中;延伸穿过源和主体的栅沟槽，漏极，设置在栅极沟槽中的栅极，具有沟槽壁的源体接触沟槽和沿着沟槽壁布置的抗穿孔植入物。制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成栅极沟槽，通过硬掩模，在栅极沟槽中沉积栅极材料，去除硬掩模以留下栅极形成具有沟槽壁并形成抗穿孔植入物的源体接触沟槽。

8. 发明授权

US07800169B2 Power MOS device 有权
标题翻译：功率MOS器件
公开(公告)号：US07800169B2
公开(公告)日：2010-09-21
申请号：US11900603
申请日：2007-09-11
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.
摘要翻译：半导体器件包括漏极，设置在漏极上的主体，具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中;延伸穿过源和主体的栅沟槽，漏极，设置在栅极沟槽中的栅极，具有沟槽壁的源体接触沟槽和沿着沟槽壁布置的抗穿孔植入物。制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成栅极沟槽，通过硬掩模，在栅极沟槽中沉积栅极材料，去除硬掩模以留下栅极形成具有沟槽壁并形成抗穿孔植入物的源体接触沟槽。

9. 发明申请

US20080001220A1 Power MOS device 有权
标题翻译：功率MOS器件
公开(公告)号：US20080001220A1
公开(公告)日：2008-01-03
申请号：US11900616
申请日：2007-09-11
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.
摘要翻译：半导体器件包括漏极，设置在漏极上的主体，具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中;延伸穿过源和主体的栅沟槽，漏极，设置在栅极沟槽中的栅极，具有沟槽壁的源体接触沟槽和沿着沟槽壁布置的抗穿孔植入物。制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成栅极沟槽，通过硬掩模，在栅极沟槽中沉积栅极材料，去除硬掩模以留下栅极形成具有沟槽壁并形成抗穿孔植入物的源体接触沟槽。

10. 发明授权

US07605425B2 Power MOS device 有权
标题翻译：功率MOS器件
公开(公告)号：US07605425B2
公开(公告)日：2009-10-20
申请号：US11900616
申请日：2007-09-11
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall.
摘要翻译：半导体器件包括漏极，设置在漏极上的主体，具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中;延伸穿过源和主体的栅沟槽，漏极，设置在栅极沟槽中的栅极，具有沟槽壁的源体接触沟槽和沿着沟槽壁布置的抗穿孔植入物。

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