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    • 2. 发明申请
    • IMPROVEMENTS IN EXTRACTING OPTICAL LABELS
    • 提取光学标签的改进
    • US20120195595A1
    • 2012-08-02
    • US13499710
    • 2009-10-20
    • Antonella BogoniMirco ScaffardiPaolo GhelfiLuca Poti
    • Antonella BogoniMirco ScaffardiPaolo GhelfiLuca Poti
    • H04J14/02
    • H04J14/08H04J14/0223H04J14/0246H04J14/025H04J14/0258H04J14/0267H04J14/0282H04Q11/0005H04Q11/0066H04Q2011/0041
    • An optical label extractor (10) comprising a non-linear optical element (12), a pump source (14) and optical filter apparatus (16). Said non-linear optical element (12) is arranged to receive optical data packets (18) at data signal wavelengths. Each said data packet comprises at least one data bit and at least one label bit. Said pump source (14) is arranged to pump said non-linear optical element such that any non-zero label bit experiences a non-linear optical effect on propagation through said non-linear optical element and an output label bit (20) comprising a respective further wavelength is thereby generated. Said optical filter apparatus (16) is arranged to receive any said output label bit from said non-linear optical element and being further arranged to prevent transmission of a part of said output label at said respective data signal wavelength and to transmit a part of said output label bit at said respective further wavelength.
    • 一种包括非线性光学元件(12),泵浦源(14)和滤光器装置(16)的光学标签提取器(10)。 所述非线性光学元件(12)被布置成以数据信号波长接收光学数据分组(18)。 每个所述数据分组包括至少一个数据位和至少一个标签位。 所述泵浦源(14)被布置成泵浦所述非线性光学元件,使得任何非零标签位对通过所述非线性光学元件的传播经历非线性光学效应,并且包括输出标签位(20) 从而产生另外的波长。 所述光学滤波器装置(16)被布置成从所述非线性光学元件接收任何所述输出标签位,并且还被布置成防止在所述各个数据信号波长处传输所述输出标签的一部分,并且传输所述 输出标签位在所述相应的另外的波长。
    • 5. 发明申请
    • Optical Circuit for Comparing Two N-Bit Binary Words
    • 用于比较两个N位二进制字的光电路
    • US20090059331A1
    • 2009-03-05
    • US12183662
    • 2008-07-31
    • Antonella BogoniLuca PotiMirco Scaffardi
    • Antonella BogoniLuca PotiMirco Scaffardi
    • G02F3/00
    • G02F3/00G02F1/3515G02F2203/70
    • An optical comparator circuit comprises a first stage comprising an optical gate which receives the signals applied to the two inputs and produces at its output an N bit signal with each bit being representative of the logical expression A XOR B for a respective pair of bits of the words A and B, a second stage which comprises an optical gate having at least two inputs, a first input being connected to the output of the first stage by an optical connection having a first time delay, and a second input being connected to the output of the first stage through (N−1) further optical connections, each further connection having a different associated time delay which is longer than the first time delay, the second stage providing at its output a signal comprising N bits, each bit corresponding to a respective bit of the signal output from the first stage at that time, and each bit having a first value if all of the inputs to the stage at that time are equal and a second value if and only if the first input differs in value from all of the second inputs, and a third stage which comprises an optical gate having two inputs, the first input being connected to the first input node of the comparator circuit and the second input being connected to the output of the second stage, the output of the third stage comprising an N-bit signal with each bit having a first value if the inputs at that time differ and a second value if the inputs at that time are the same, the presence of the second value in the output being indicative of word A being greater than word B.
    • 光学比较器电路包括第一级,其包括光栅,其接收施加到两个输入的信号,并在其输出端产生一个N位信号,其中每个位表示逻辑表达式A XOR B,用于相应的位对 字A和B,第二级,其包括具有至少两个输入的光栅,第一输入通过具有第一时间延迟的光学连接连接到第一级的输出,第二输入连接到输出 (N-1)个进一步的光学连接,每个另外的连接具有比第一时间延迟更长的不同的相关时间延迟,第二级在其输出端提供包括N位的信号,每个位对应于 在该时间从第一级输出的信号的相应位,如果当时的所有阶段的所有输入都相等,并且每个位具有第一值,并且当且仅当 第一输入的值与所有第二输入不同,第三级包括具有两个输入的光栅,第一输入连接到比较器电路的第一输入节点,第二输入端连接到 第二级,如果第二级的输入相同,那么第三级的输出包括一个N位信号,其中每个位具有第一值,如果该时间的输入相同,则第二值如果该时间的输入相同,则存在第二值 在输出中表示词A大于词B.
    • 6. 发明申请
    • ALL OPTICAL PROCESSING CIRCUIT FOR CONFLICT RESOLUTION AND SWITCH CONFIGURATION IN A 2X2 OPTICAL NODE
    • 所有用于2X2光学节点中的冲突分辨率和开关配置的光学处理电路
    • US20100208317A1
    • 2010-08-19
    • US12597784
    • 2007-05-01
    • Antonella BogoniLuca PotiMirco Scaffardi
    • Antonella BogoniLuca PotiMirco Scaffardi
    • G02F3/00
    • H04Q11/0005G02F3/00H04Q11/0066H04Q2011/0015H04Q2011/002H04Q2011/0039H04Q2011/0041H04Q2011/005H04Q2011/0052H04Q2011/0058
    • An optical processing circuit, such as a combinatorial network, comprises an arrangement of optical logic gates suitable for use in combination with a switched optical node of the kind having at least first and second input ports and two output ports, the node being configurable into either a cross or a bar configuration, and in which the optical processing circuit is arranged so as to receive at least three optical input signals which respectively comprise a packet identifier signal PIH which identifies whether or not a first input signal is present at the first input port of the switched optical node, the first input port being assigned a higher priority than the second input port, a first destination address AH indicating the output port of the switched optical node to which a first information carrying signal, received at the first input port, is intended to be passed, and a second destination address AL indicating the output port of the switched optical node to which a second information carrying signal, received at the second input port, is intended to be passed, and in which the processing circuit is configured to generate from these three optical input signals the following optical output signals: a contention resolution control (CRC) signal which has a first value if a routing conflict is present and a second if it is not; and a switch control generation (SCG) signal indicating whether the associated switched optical node is to be set in a cross or bar configuration.
    • 诸如组合网络的光学处理电路包括适于与具有至少第一和第二输入端口和两个输出端口的类型的交换光学节点组合使用的光学逻辑门的布置,该节点可配置为 交叉或条形配置,并且其中所述光学处理电路被布置为接收至少三个光学输入信号,所述至少三个光学输入信号分别包括分组标识符信号PIH,所述分组标识符信号表示第一输入信号是否存在于所述第一输入端口 所述第一输入端口被分配比所述第二输入端口更高的优先级;第一目的地地址AH,其指示在所述第一输入端口处接收到的第一信息携带信号的所述交换光节点的输出端口, 以及第二目的地地址AL,其指示切换的光节点的输出端口,其中具有第二信息 旨在通过在第二输入端口接收的定位承载信号,并且其中处理电路被配置为从这三个光学输入信号产生以下光学输出信号:竞争解决控制(CRC)信号,其具有 如果存在路由冲突,则为第一个值,如果不存在路由冲突则为第二个值; 以及指示是否将相关联的交换光节点设置为交叉或条形配置的开关控制产生(SCG)信号。
    • 9. 发明授权
    • All optical processing circuit for conflict resolution and switch configuration in a 2×2 optical node
    • 用于2×2光节点中的冲突解决和开关配置的所有光学处理电路
    • US09137591B2
    • 2015-09-15
    • US12597784
    • 2007-05-01
    • Antonella BogoniLuca PotiMirco Scaffardi
    • Antonella BogoniLuca PotiMirco Scaffardi
    • G02F3/00H04Q11/00
    • H04Q11/0005G02F3/00H04Q11/0066H04Q2011/0015H04Q2011/002H04Q2011/0039H04Q2011/0041H04Q2011/005H04Q2011/0052H04Q2011/0058
    • An optical processing circuit, such as a combinatorial network, comprises an arrangement of optical logic gates suitable for use in combination with a switched optical node of the kind having at least first and second input ports and two output ports, the node being configurable into either a cross or a bar configuration, and in which the optical processing circuit is arranged so as to receive at least three optical input signals which respectively comprise a packet identifier signal PIH which identifies whether or not a first input signal is present at the first input port of the switched optical node, the first input port being assigned a higher priority than the second input port, a first destination address AH indicating the output port of the switched optical node to which a first information carrying signal, received at the first input port, is intended to be passed, and a second destination address AL indicating the output port of the switched optical node to which a second information carrying signal, received at the second input port, is intended to be passed, and in which the processing circuit is configured to generate from these three optical input signals the following optical output signals: a contention resolution control (CRC) signal which has a first value if a routing conflict is present and a second if it is not; and a switch control generation (SCG) signal indicating whether the associated switched optical node is to be set in a cross or bar configuration.
    • 诸如组合网络的光学处理电路包括适于与具有至少第一和第二输入端口和两个输出端口的类型的交换光学节点组合使用的光学逻辑门的布置,该节点可配置为 交叉或条形配置,并且其中所述光学处理电路被布置为接收至少三个光学输入信号,所述至少三个光学输入信号分别包括分组标识符信号PIH,所述分组标识符信号表示第一输入信号是否存在于所述第一输入端口 所述第一输入端口被分配比所述第二输入端口更高的优先级;第一目的地地址AH,其指示在所述第一输入端口处接收到的第一信息携带信号的所述交换光节点的输出端口, 以及第二目的地地址AL,其指示切换的光节点的输出端口,其中具有第二信息 旨在通过在第二输入端口接收的定位承载信号,并且其中处理电路被配置为从这三个光学输入信号产生以下光学输出信号:竞争解决控制(CRC)信号,其具有 如果存在路由冲突,则为第一个值,如果不存在路由冲突则为第二个值; 以及指示是否将相关联的交换光节点设置为交叉或条形配置的开关控制产生(SCG)信号。
    • 10. 发明申请
    • OPTICAL ANALOGUE TO DIGITAL CONVERTER
    • 数字转换器的光学模拟
    • US20110234436A1
    • 2011-09-29
    • US13127085
    • 2008-10-31
    • Antonella BogoniFrancesco FresiEmma LazzeriMirco ScaffardiLuca Poti
    • Antonella BogoniFrancesco FresiEmma LazzeriMirco ScaffardiLuca Poti
    • H03M1/12
    • G02F7/00G02F1/3515G02F2203/70
    • An analogue to digital converter (100) is arranged to receive and process an analogue optical input signal (110) to produce an N bit digital optical output signal (140) quantised to 2N levels, where N is greater than or equal to 2. The converter (100) has an input (115) for receiving the optical input signal (110) and N processing channels (131, 132, 133) which arc each coupled to the input, at least one of said processing channels comprising an optical processing circuit (201, 202, 203, 204, 205, 206, 207) arranged to generate a plurality of digital optical output signals. The optical processing circuit is arranged to change the state of each digital optical output signal corresponding to a respective different value of the analogue optical input signal, and an optical combining circuit (301, 302, 303, 304) for combining the optical output signals in signal order to generate one bit of the N-bit digital optical signal.
    • 模拟数字转换器(100)被布置为接收和处理模拟光输入信号(110)以产生量化为2N级的N位数字光输出信号(140),其中N大于或等于2。 转换器(100)具有用于接收光输入信号(110)的输入端(115)和各自耦合到输入端的N个处理通道(131,132,133),所述处理通道中的至少一个包括光处理电路 (201,202,203,204,205,206,207),被布置成产生多个数字光输出信号。 光处理电路被配置为改变对应于模拟光输入信号的相应不同值的每个数字光输出信号的状态,以及光合成电路(301,302,303,304),用于将光输出信号 信号顺序产生一位N位数字光信号。