专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080036486A1 INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION 失效
公开(公告)号：US20080036486A1
公开(公告)日：2008-02-14
申请号：US11876066
申请日：2007-10-22
申请人： Anne Gattiker , David Grosch , Marc Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul Zuchowski
发明人： Anne Gattiker , David Grosch , Marc Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/3008 , G01R31/31858
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

2. 发明申请

US20060071653A1 Integrated circuit testing methods using well bias modification 失效
标题翻译：集成电路测试方法采用偏置修正
公开(公告)号：US20060071653A1
公开(公告)日：2006-04-06
申请号：US10539247
申请日：2003-02-20
申请人： Anne Gattiker , David Grosch , Marc Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul Zuchowski
发明人： Anne Gattiker , David Grosch , Marc Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul Zuchowski
IPC分类号： G01R19/00
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/2856 , G01R31/3004 , G01R31/3008
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.
摘要翻译：测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。此外，这些方法在应力测试期间提供更有效的应力。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

3. 发明授权

US07400162B2 Integrated circuit testing methods using well bias modification 失效
标题翻译：集成电路测试方法采用偏置修正
公开(公告)号：US07400162B2
公开(公告)日：2008-07-15
申请号：US10539247
申请日：2003-02-20
申请人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/2856 , G01R31/3004 , G01R31/3008
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.
摘要翻译：测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。此外，这些方法在应力测试期间提供更有效的应力。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

4. 发明授权

US07564256B2 Integrated circuit testing methods using well bias modification 失效
标题翻译：集成电路测试方法采用偏置修正
公开(公告)号：US07564256B2
公开(公告)日：2009-07-21
申请号：US12119834
申请日：2008-05-13
申请人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/3008 , G01R31/31858
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.
摘要翻译：测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。此外，这些方法在应力测试期间提供更有效的应力。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

5. 发明授权

US07486098B2 Integrated circuit testing method using well bias modification 失效
标题翻译：集成电路测试方法采用井偏置修正
公开(公告)号：US07486098B2
公开(公告)日：2009-02-03
申请号：US11876066
申请日：2007-10-22
申请人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/3008 , G01R31/31858
摘要： A method for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The method improves the resolution of IDDQ testing and diagnosis by modifying well bias during testing. The method applies to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the method relies on using the well bias to change transistor threshold voltages.
摘要翻译：一种用于测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过修改测试过程中的良好偏差来提高IDDQ测试和诊断的分辨率。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开布线的IC，允许在测试期间对阱电位进行外部控制（40）。通常，该方法依赖于使用阱偏压来改变晶体管阈值电压。

6. 发明申请

US20080211531A1 INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION 失效
公开(公告)号：US20080211531A1
公开(公告)日：2008-09-04
申请号：US12119834
申请日：2008-05-13
申请人： Anne E. Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne E. Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/3008 , G01R31/31858
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

7. 发明授权

US07759960B2 Integrated circuit testing methods using well bias modification 失效
标题翻译：集成电路测试方法采用偏置修正
公开(公告)号：US07759960B2
公开(公告)日：2010-07-20
申请号：US12103906
申请日：2008-04-16
申请人： Anne E. Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne E. Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/2856 , G01R31/3004 , G01R31/3008
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.
摘要翻译：测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。此外，这些方法在应力测试期间提供更有效的应力。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

8. 发明申请

US20080211530A1 INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION 失效
标题翻译：集成电路测试方法使用良好的偏差修正
公开(公告)号：US20080211530A1
公开(公告)日：2008-09-04
申请号：US12103906
申请日：2008-04-16
申请人： Anne E. Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne E. Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/2856 , G01R31/3004 , G01R31/3008
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.
摘要翻译：测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。此外，这些方法在应力测试期间提供更有效的应力。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

9. 发明授权

US5942911A Electric field test of integrated circuit component 失效
标题翻译：集成电路元件的电场测试
公开(公告)号：US5942911A
公开(公告)日：1999-08-24
申请号：US123149
申请日：1998-07-27
申请人： Franco Motika , Paul Motika , Phil Nigh
发明人： Franco Motika , Paul Motika , Phil Nigh
IPC分类号： G01R31/28 , G01R31/312 , G01R31/26
CPC分类号： G01R31/312 , G01R31/2851
摘要： The manufacture of an integrated circuit chip includes testing the integrated circuit while an external electric field is applied to the integrated circuit to facilitate detection of open circuit type defects. The electric field may be provided by applying a high potential to a plate parallel to a plane of the integrated circuit or by applying a high potential to a probe and moving the probe across the surface of the integrated circuit chip to obtain information regarding the location of the defect. Use of a probe type electric field generator allows the approximate position of the defect to be determined. The invention enhances current testing and diagnostics methods for wafers, chips, and integrated circuit packages by allowing detection of floating net defects during other conventional tests.
摘要翻译：集成电路芯片的制造包括测试集成电路，同时将外部电场施加到集成电路以便于检测开路型缺陷。可以通过向平行于集成电路的平面的板施加高电位或者通过向探针施加高电位并将探针移动跨越集成电路芯片的表面来获得有关位置的信息来提供电场缺陷。使用探针型电场发生器可以确定缺陷的大致位置。本发明通过在其他常规测试期间允许检测浮动净缺陷来增强晶片，芯片和集成电路封装的电流测试和诊断方法。

10. 发明授权

US5982189A Built-in dynamic stress for integrated circuits 失效
标题翻译：内置动态应力集成电路
公开(公告)号：US5982189A
公开(公告)日：1999-11-09
申请号：US856414
申请日：1997-05-14
申请人： Franco Motika , Phil Nigh , John Shushereba
发明人： Franco Motika , Phil Nigh , John Shushereba
IPC分类号： G01R31/30 , G01R27/26
CPC分类号： G01R31/30
摘要： A built-in stress circuit for an integrated circuit that has a frequency generator, at least one self-test circuit, a temperature regulator and a controller is disclosed. The frequency generator receives a reference clock and an adjusted temperature frequency from the temperature regulator and outputs the test frequencies needed for the self-test circuits. The self-test circuits, which are coupled to the frequency generator, receive the test frequencies and dissipate power as the self-test circuits are being used. The temperature regulator, which is coupled to the self-test circuits and the frequency generator, senses the power dissipated (i.e., the temperature), adjusts a temperature frequency corresponding to the temperature desired, and outputs the adjusted temperature frequency. The controller, which is coupled to the frequency generator, the self-test circuits, and the temperature regulator, provides the control data necessary for testing both electrical and thermal stress conditions.
摘要翻译：公开了一种用于具有频率发生器，至少一个自检电路，温度调节器和控制器的集成电路的内置应力电路。频率发生器从温度调节器接收参考时钟和调整的温度频率，并输出自检电路所需的测试频率。耦合到频率发生器的自测电路在使用自检电路时接收测试频率并耗散功率。耦合到自检电路和频率发生器的温度调节器感测功率消耗（即，温度），调节对应于期望温度的温度频率，并输出调节的温度频率。耦合到频率发生器，自检电路和温度调节器的控制器提供测试电和热应力条件所需的控制数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式