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1. 发明授权

US08555035B1 Conflict-free register allocation using a multi-bank register file with input operand alignment 有权
标题翻译：使用输入操作数对齐的多存储器寄存器文件进行无冲突寄存器分配
公开(公告)号：US08555035B1
公开(公告)日：2013-10-08
申请号：US12831953
申请日：2010-07-07
申请人： Anjul Patney , William J. Dally
发明人： Anjul Patney , William J. Dally
IPC分类号： G06F9/44
CPC分类号： G06F8/441
摘要： One embodiment of the present invention sets forth a technique for using a multi-bank register file that reduces the size of or eliminates a switch and/or staging registers that are used to gather input operands for instructions. Each function unit input may be directly connected to one bank of the multi-bank register file with neither a switch nor a staging register. A compiler or register allocation unit ensures that the register file accesses for each instruction are conflict-free (no instruction can access the same bank more than once in the same cycle). The compiler or register allocation unit may also ensure that the register file accesses for each instruction are also aligned (each input of a function unit can only come from the bank connected to that input).
摘要翻译：本发明的一个实施例提出了一种使用减少用于收集用于指令的输入操作数的开关和/或分段寄存器的大小或消除的多存储体寄存器堆的技术。每个功能单元输入可以直接连接到多存储区寄存器文件的一行，既不带有开关也不是暂存寄存器。编译器或寄存器分配单元确保每个指令的寄存器文件访问是无冲突的（没有指令可以在同一周期内多次访问同一个存储体）。编译器或寄存器分配单元还可以确保每个指令的寄存器文件访问也被对齐（功能单元的每个输入只能来自连接到该输入的存储体）。

2. 发明授权

US08832671B1 Conflict-free register allocation 有权
标题翻译：无冲突的注册分配
公开(公告)号：US08832671B1
公开(公告)日：2014-09-09
申请号：US12831957
申请日：2010-07-07
申请人： Anjul Patney , William J. Dally
发明人： Anjul Patney , William J. Dally
IPC分类号： G06F9/44 , G06F9/30 , G06F9/45
CPC分类号： G06F9/3012 , G06F8/441 , G06F9/384
摘要： One embodiment of the present invention sets forth a technique for using a multi-bank register file that reduces the size of or eliminates a switch and/or staging registers that are used to gather input operands for instructions. Each function unit input may be directly connected to one bank of the multi-bank register file with neither a switch nor a staging register. A compiler or register allocation unit ensures that the register file accesses for each instruction are conflict-free (no instruction can access the same bank more than once in the same cycle). The compiler or register allocation unit may also ensure that the register file accesses for each instruction are also aligned (each input of a function unit can only come from the bank connected to that input).
摘要翻译：本发明的一个实施例提出了一种使用减少用于收集用于指令的输入操作数的开关和/或分段寄存器的大小或消除的多存储体寄存器堆的技术。每个功能单元输入可以直接连接到多存储区寄存器文件的一行，既不带有开关也不是暂存寄存器。编译器或寄存器分配单元确保每个指令的寄存器文件访问是无冲突的（没有指令可以在同一周期内多次访问同一个存储体）。编译器或寄存器分配单元还可以确保每个指令的寄存器文件访问也被对齐（功能单元的每个输入只能来自连接到该输入的存储体）。

3. 发明授权

US08860742B2 Coverage caching 有权
标题翻译：覆盖缓存
公开(公告)号：US08860742B2
公开(公告)日：2014-10-14
申请号：US13462759
申请日：2012-05-02
申请人： Michael C. Shebanow , Anjul Patney
发明人： Michael C. Shebanow , Anjul Patney
IPC分类号： G09G5/36 , G09G5/00
CPC分类号： G09G5/36 , G06T11/40 , G09G5/363
摘要： A technique for caching coverage information for edges that are shared between adjacent graphics primitives may reduce the number of times a shared edge is rasterized. Consequently, power consumed during rasterization may be reduced. During rasterization of a first graphics primitive coverage information is generated that (1) indicates cells within a sampling grid that are entirely outside an edge of the first graphics primitive and (2) indicates cells within the sampling grid that are intersected by the edge and are only partially covered by the first graphics primitive. The coverage information for the edge is stored in a cache. When a second graphics primitive is rasterized that shares the edge with the first graphics primitive, the coverage information is read from the cache instead of being recomputed.
摘要翻译：用于缓存在相邻图形基元之间共享的边缘的覆盖信息的技术可以减少共享边缘被光栅化的次数。因此，可以减少光栅化期间消耗的功率。在第一图形基元的光栅化期间，产生覆盖信息，其中（1）表示采样网格内的完全在第一图形基元的边缘外部的单元，以及（2）表示采样网格内与边缘相交的单元格，仅部分被第一个图形原始覆盖。边缘的覆盖信息存储在缓存中。当与第一图形原语共享边缘的第二图形基元被光栅化时，从高速缓存读取覆盖信息，而不是被重新计算。

4. 发明申请

US20120281004A1 COVERAGE CACHING 有权
标题翻译：覆盖缓存
公开(公告)号：US20120281004A1
公开(公告)日：2012-11-08
申请号：US13462759
申请日：2012-05-02
申请人： Michael C. Shebanow , Anjul Patney
发明人： Michael C. Shebanow , Anjul Patney
IPC分类号： G09G5/36
CPC分类号： G09G5/36 , G06T11/40 , G09G5/363
摘要： A technique for caching coverage information for edges that are shared between adjacent graphics primitives may reduce the number of times a shared edge is rasterized. Consequently, power consumed during rasterization may be reduced. During rasterization of a first graphics primitive coverage information is generated that (1) indicates cells within a sampling grid that are entirely outside an edge of the first graphics primitive and (2) indicates cells within the sampling grid that are intersected by the edge and are only partially covered by the first graphics primitive. The coverage information for the edge is stored in a cache. When a second graphics primitive is rasterized that shares the edge with the first graphics primitive, the coverage information is read from the cache instead of being recomputed.
摘要翻译：用于缓存在相邻图形基元之间共享的边缘的覆盖信息的技术可以减少共享边缘被光栅化的次数。因此，可以减少光栅化期间消耗的功率。在第一图形基元的光栅化期间，产生覆盖信息，其中（1）表示采样网格内的完全在第一图形基元的边缘外部的单元，以及（2）表示采样网格内与边缘相交的单元格，仅部分被第一个图形原始覆盖。边缘的覆盖信息存储在缓存中。当与第一图形原语共享边缘的第二图形基元被光栅化时，从高速缓存读取覆盖信息，而不是被重新计算。

5. 发明申请

US20120280992A1 GRID WALK SAMPLING 审中-公开
标题翻译：网路采样
公开(公告)号：US20120280992A1
公开(公告)日：2012-11-08
申请号：US13461666
申请日：2012-05-01
申请人： Michael C. Shebanow , Anjul Patney
发明人： Michael C. Shebanow , Anjul Patney
IPC分类号： G06T17/00
CPC分类号： G06T11/40
摘要： The grid walk sampling technique is an efficient sampling algorithm aimed at optimizing the cost of triangle rasterization for modern graphics workloads. Grid walk sampling is an iterative rasterization algorithm that intelligently tests the intersection of triangle edges with multi-cell grids, determining coverage for a grid cell while identifying other cells in the grid that are either fully covered or fully uncovered by the triangle. Grid walk sampling rasterizes triangles using fewer computations and simpler computations compared with conventional highly parallel rasterizers. Therefore, a rasterizer employing grid walk sampling may compute sample coverage of triangles more efficiently in terms of power and circuitry die area compared with conventional highly parallel rasterizers.
摘要翻译：网格行走采样技术是一种高效的采样算法，旨在优化现代图形工作负载的三角形光栅化成本。网格行走采样是一种迭代光栅化算法，它可以智能地测试三角形边缘与多单元格网格的交点，确定网格单元格的覆盖范围，同时识别网格中由三角形完全覆盖或完全未覆盖的其他单元格。与传统的高度平行光栅化器相比，栅格行走采样使用更少的计算和更简单的计算来对三角形进行光栅化。因此，与传统的高度平行光栅化器相比，使用栅格行走采样的光栅化器可以在功率和电路裸片面积方面更有效地计算三角形的样本覆盖。

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