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1. 发明申请

US20130262718A1 Adaptive Queuing of a Cache for a Processing Element 有权
标题翻译：处理元素缓存的自适应队列
公开(公告)号：US20130262718A1
公开(公告)日：2013-10-03
申请号：US13436337
申请日：2012-03-30
申请人： Anil Vasudevan , Glenn J. Hinton , Yadong Li
发明人： Anil Vasudevan , Glenn J. Hinton , Yadong Li
IPC分类号： G06F3/00
CPC分类号： G06F12/084 , G06F5/10 , H04L49/90
摘要： Examples are disclosed for establishing a window for a queue structure maintained in a cache for a processing element for a network device. The processing element may be configured to operate in cooperation with an input/output device such as a network interface card. In some of these examples, the window may include portions of the queue structure having identifiers to active allocated buffers maintained in memory for the network device. The active allocated buffers may be configured to maintain or store data received or to be forwarded by the input/output device. For these examples, the window may be adjusted based on information gathered while the identifiers are read from or written to the portions of the queue structure.
摘要翻译：公开了用于建立用于网络设备的处理元件的高速缓存中维护的队列结构的窗口的示例。处理元件可以被配置为与诸如网络接口卡的输入/输出设备协作操作。在这些示例中的一些示例中，窗口可以包括具有对于网络设备的存储器中维护的主动分配缓冲区的标识符的队列结构的部分。活动分配的缓冲器可以被配置为维护或存储由输入/输出设备接收或要转发的数据。对于这些示例，可以基于从标识符从队列结构的部分读取或写入标识符时收集的信息来调整窗口。

2. 发明授权

US09146873B2 Adaptive queuing of a cache for a processing element 有权
标题翻译：用于处理元素的缓存的自适应排队
公开(公告)号：US09146873B2
公开(公告)日：2015-09-29
申请号：US13436337
申请日：2012-03-30
申请人： Anil Vasudevan , Glenn J. Hinton , Yadong Li
发明人： Anil Vasudevan , Glenn J. Hinton , Yadong Li
IPC分类号： G06F3/00 , G06F12/08 , H04L12/861 , G06F5/10
CPC分类号： G06F12/084 , G06F5/10 , H04L49/90
摘要： Examples are disclosed for establishing a window for a queue structure maintained in a cache for a processing element for a network device. The processing element may be configured to operate in cooperation with an input/output device such as a network interface card. In some of these examples, the window may include portions of the queue structure having identifiers to active allocated buffers maintained in memory for the network device. The active allocated buffers may be configured to maintain or store data received or to be forwarded by the input/output device. For these examples, the window may be adjusted based on information gathered while the identifiers are read from or written to the portions of the queue structure.
摘要翻译：公开了用于建立用于网络设备的处理元件的高速缓存中维护的队列结构的窗口的示例。处理元件可以被配置为与诸如网络接口卡的输入/输出设备协作操作。在这些示例中的一些示例中，窗口可以包括具有对于网络设备的存储器中维护的主动分配缓冲区的标识符的队列结构的部分。活动分配的缓冲器可以被配置为维护或存储由输入/输出设备接收或要转发的数据。对于这些示例，可以基于从标识符从队列结构的部分读取或写入标识符时收集的信息来调整窗口。

3. 发明授权

US09009367B2 Adaptive interrupt moderation 有权
标题翻译：自适应中断节制
公开(公告)号：US09009367B2
公开(公告)日：2015-04-14
申请号：US13566298
申请日：2012-08-03
申请人： Yadong Li , Linden Cornett , Manasi Deval , Anil Vasudevan , Parthasarathy Sarangam
发明人： Yadong Li , Linden Cornett , Manasi Deval , Anil Vasudevan , Parthasarathy Sarangam
IPC分类号： G06F3/00 , G06F15/16 , G06F13/24
CPC分类号： G06F13/24 , H04L69/165
摘要： Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.
摘要翻译：通常，本公开涉及自适应中断调节。方法可以包括：至少部分地基于与每个连接相关联的连接标识符，由主机设备确定主机设备与一个或多个链路伙伴之间的连接数; 由所述主机设备至少部分地基于多个连接来确定新的中断率; 通过所述主机设备更新具有与所述新中断速率相关的值的中断调节定时器; 并配置中断调节定时器以允许以新的中断速率发生中断。

4. 发明申请

US20140040514A1 ADAPTIVE INTERRUPT MODERATION 有权
标题翻译：自适应中断调制
公开(公告)号：US20140040514A1
公开(公告)日：2014-02-06
申请号：US13566298
申请日：2012-08-03
申请人： Yadong Li , Linden Cornett , Manasi Deval , Anil Vasudevan , Parthasarathy Sarangam
发明人： Yadong Li , Linden Cornett , Manasi Deval , Anil Vasudevan , Parthasarathy Sarangam
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , H04L69/165
摘要： Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.
摘要翻译：通常，本公开涉及自适应中断调节。方法可以包括：至少部分地基于与每个连接相关联的连接标识符，由主机设备确定主机设备与一个或多个链路伙伴之间的连接数; 由所述主机设备至少部分地基于多个连接来确定新的中断率; 通过所述主机设备更新具有与所述新中断速率相关的值的中断调节定时器; 并配置中断调节定时器以允许以新的中断速率发生中断。

5. 发明申请

US20150009823A1 CREDIT FLOW CONTROL FOR ETHERNET 有权
标题翻译：以太网信用流量控制
公开(公告)号：US20150009823A1
公开(公告)日：2015-01-08
申请号：US14313740
申请日：2014-06-24
申请人： Ilango Ganga , Alain Gravel , Anil Vasudevan , Radia Perlman , Greg Regnier , Anil Vasudevan , Hugh Wilkinson
发明人： Ilango Ganga , Alain Gravel , Anil Vasudevan , Radia Perlman , Greg Regnier , Anil Vasudevan , Hugh Wilkinson
IPC分类号： H04L12/801 , H04L12/851
CPC分类号： H04L47/2441 , Y02D30/30 , Y02D30/32
摘要： One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.
摘要翻译：一个实施例提供了一种用于对使用以太网通信协议与链路伙伴通信的网络节点启用基于类的信用流量控制的方法。该方法包括从链路伙伴接收控制帧。所述控制帧包括至少一个用于指定至少一个业务类别的信用的字段，并且所述信用是基于与所述至少一个业务类别相关联的接收缓冲器中的可用空间。所述方法还包括基于所述信用向所述链路伙伴发送数据分组，所述数据分组与所述至少一个业务类别相关联的所述数据分组。

6. 发明申请

US20140171429A1 BICYCLIC INHIBITORS OF ALK 审中-公开
标题翻译：双酚A抑制剂
公开(公告)号：US20140171429A1
公开(公告)日：2014-06-19
申请号：US13979388
申请日：2012-01-20
申请人： Anil Vasudevan , Thomas Dale Penning , Huanming Chen , Bo Liang , Shaohui Wang , Zhongqiang Zhao , Dikun Chai , Leifu Yang , Yingxiang Gao , Marina Pliushchev
发明人： Anil Vasudevan , Thomas Dale Penning , Huanming Chen , Bo Liang , Shaohui Wang , Zhongqiang Zhao , Dikun Chai , Leifu Yang , Yingxiang Gao , Marina Pliushchev
IPC分类号： C07D471/04
CPC分类号： C07D471/04 , C07D401/12
摘要： The present invention relates to compounds of formula (1) or pharmaceutical acceptable salts, Formula (1) wherein R1, R2, R3, X, Y, Z, A, B, G1, m, and n are defined in the description. The present invention relates also to compositions containing said compounds which are useful for inhibiting kinases such as ALK and methods of treating diseases such as cancer.
摘要翻译：本发明涉及式（1）化合物或其药学上可接受的盐，式（1）其中R 1，R 2，R 3，X，Y，Z，A，B，G 1，m和n在说明书中定义。本发明还涉及含有可用于抑制ALK等激酶的化合物的组合物和治疗诸如癌症的疾病的方法。

7. 发明申请

US20140161122A1 NETWORK DEVICE SELECTION 有权
标题翻译：网络设备选择
公开(公告)号：US20140161122A1
公开(公告)日：2014-06-12
申请号：US13995241
申请日：2011-11-22
申请人： Anil Vasudevan
发明人： Anil Vasudevan
IPC分类号： H04L12/775
CPC分类号： H04L45/58 , H04L49/25 , H04L49/351 , H04L49/70
摘要： An embodiment may include circuitry that may be capable of selecting, from network devices, at least one network device to which at least one packet is to be transmitted. The network devices may be associated, at least in part, with each other in at least one link aggregation. The circuitry may select the at least one network device based at least in part upon a relative degree of affinity that the at least one network device may have with respect to at least one central processing unit (CPU) socket that may be associated, at least in part, with at least one flow to which the at least one packet may belong. The relative degree of affinity may be relative to respective degrees of affinity that one or more others of the network devices may have with respect to the at least one CPU socket. Many modifications are possible.
摘要翻译：实施例可以包括可以能够从网络设备选择要发送至少一个分组的至少一个网络设备的电路。网络设备至少部分地可以在至少一个链路聚合中彼此相关联。该电路可以至少部分地基于至少一个网络设备可能相对于至少一个中央处理单元（CPU）插座具有的至少一个中心处理单元（CPU）插座的相对程度来选择该至少一个网络设备，至少一个中央处理单元部分地与至少一个分组可以属于的至少一个流。亲和度的相对程度可以相对于网络设备中的一个或多个其他网络设备相对于至少一个CPU插座可能具有的相对程度的亲和度。许多修改是可能的。

8. 发明申请

US20130227161A1 TRANSMIT SCALING USING MULTIPLE QUEUES 有权
公开(公告)号：US20130227161A1
公开(公告)日：2013-08-29
申请号：US13771839
申请日：2013-02-20
申请人： Anil Vasudevan , Sujoy Sen , Partha Sarangam
发明人： Anil Vasudevan , Sujoy Sen , Partha Sarangam
IPC分类号： H04L12/70
CPC分类号： H04L47/622 , H04L47/2475 , H04L49/90 , H04L49/9047 , H04L49/9063 , H04L49/9094 , H04L69/12 , H04L69/32
摘要： According to some embodiments, it may be determined, at a first processing element of a device with a plurality of processing elements, that first data is to be transmitted in association with a first network connection. A first entry associated with the first data may then be stored into a first of a plurality of transmit queues. It may subsequently be determined, at a second processing element of the device, that second data is to be transmitted in association with the first network connection. A second entry associated with the second data may then be stored into a second of the plurality of transmit queues.

9. 发明申请

US20130132636A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 审中-公开
公开(公告)号：US20130132636A1
公开(公告)日：2013-05-23
申请号：US13690931
申请日：2012-11-30
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/42
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

10. 发明申请

US20130091317A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 审中-公开
公开(公告)号：US20130091317A1
公开(公告)日：2013-04-11
申请号：US13691016
申请日：2012-11-30
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/40
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

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