专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07382660B2 Method for accessing a multilevel nonvolatile memory device of the flash NAND type 有权
标题翻译：用于访问闪存NAND型的多级非易失性存储器件的方法
公开(公告)号：US07382660B2
公开(公告)日：2008-06-03
申请号：US11458904
申请日：2006-07-20
申请人： Angelo Bovino , Vincenzo Altieri , Roberto Ravasio , Rino Micheloni , Mario De Matteis
发明人： Angelo Bovino , Vincenzo Altieri , Roberto Ravasio , Rino Micheloni , Mario De Matteis
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C2211/5641
摘要： Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.
摘要翻译：多级编程允许通过从第二位单独编程第一位来在选定单元中写入第一位和第二位。第一位的编程确定从第一阈值电平转换到第二阈值电平。第二位的编程需要初步读取以检测第一位是否已被修改，如果第一位已被修改并执行第二写入步骤，执行第一写入步骤以使单元进入第三阈值电压，以使所选择的如果第一位未被修改，则将单元转换为不同于第三阈值电平的第四阈值电压。为了增加读取和编程的可靠性，在第二部分的初步读取期间，读取结果被迫对应于第一阈值水平。

2. 发明申请

US20070047299A1 METHOD FOR ACCESSING A MULTILEVEL NONVOLATILE MEMORY DEVICE OF THE FLASH NAND TYPE 有权
标题翻译：用于访问闪存NAND类型的多个非易失性存储器件的方法
公开(公告)号：US20070047299A1
公开(公告)日：2007-03-01
申请号：US11458904
申请日：2006-07-20
申请人： Angelo Bovino , Vincenzo Altieri , Roberto Ravasio , Rino Micheloni , Mario De Matteis
发明人： Angelo Bovino , Vincenzo Altieri , Roberto Ravasio , Rino Micheloni , Mario De Matteis
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C2211/5641
摘要： Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.
摘要翻译：多级编程允许通过从第二位单独编程第一位来在选定单元中写入第一位和第二位。第一位的编程确定从第一阈值电平转换到第二阈值电平。第二位的编程需要初步读取以检测第一位是否已被修改，如果第一位已被修改并执行第二写入步骤，执行第一写入步骤以使单元进入第三阈值电压，以使所选择的如果第一位未被修改，则将单元转换为不同于第三阈值电平的第四阈值电压。为了增加读取和编程的可靠性，在第二部分的初步读取期间，读取结果被迫对应于第一阈值水平。

3. 发明申请

US20060059406A1 Memory with embedded error correction codes 有权
公开(公告)号：US20060059406A1
公开(公告)日：2006-03-16
申请号：US11221584
申请日：2005-09-08
申请人： Rino Micheloni , Roberto Ravasio , Angelo Bovino , Vincenzo Altieri
发明人： Rino Micheloni , Roberto Ravasio , Angelo Bovino , Vincenzo Altieri
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code circuit for calculating an ECC. The memory is configured to be responsive to external commands for controlling the operation of the ECC circuit for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.

4. 发明授权

US07581153B2 Memory with embedded error correction codes 有权
标题翻译：具有嵌入式纠错码的内存
公开(公告)号：US07581153B2
公开(公告)日：2009-08-25
申请号：US11221584
申请日：2005-09-08
申请人： Rino Micheloni , Roberto Ravasio , Angelo Bovino , Vincenzo Altieri
发明人： Rino Micheloni , Roberto Ravasio , Angelo Bovino , Vincenzo Altieri
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code circuit for calculating an ECC. The memory is configured to be responsive to external commands for controlling the operation of the ECC circuit for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.
摘要翻译：内存有一条总线用于数据，地址和命令。数据寄存器耦合到总线以存储写入存储器和从存储器读取的数据，命令寄存器耦合到总线以接收存储器命令，并且地址寄存器耦合到总线以寻址存储器。存储器还包括用于计算ECC的纠错码电路。存储器被配置为响应于用于控制ECC电路的操作的外部命令，用于读取或写入与控制存储器数据的读取或写入的外部命令分离的ECC。存储器还可以包括状态寄存器，其存储关于ECC的通过或失败的信息。

5. 发明申请

US20070030735A1 Page buffer circuit and method for multi-level NAND programmable memories 有权
标题翻译：页面缓冲电路和多级NAND可编程存储器的方法
公开(公告)号：US20070030735A1
公开(公告)日：2007-02-08
申请号：US11495874
申请日：2006-07-28
申请人： Luca Crippa , Chiara Missiroli , Roberto Ravasio , Rino Micheloni , Angelo Bovino
发明人： Luca Crippa , Chiara Missiroli , Roberto Ravasio , Rino Micheloni , Angelo Bovino
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C2211/5621 , G11C2211/5642 , G11C2216/14
摘要： A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cell sets. The read/program unit includes enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits of the selected memory cell and an existing data value already stored in the second group of data bits of the selected memory cell. The enabling means includes reading means for retrieving the existing data value, means for receiving an indication of the target data value, combining means for combining the received target data value with the retrieved existing data value, thereby modifying said indication of the target data value so as to obtain a modified indication. Conditioning means in the combining means condition a potential of the coupling line based on the existing data value and the modified indication so as to cause the coupling line to take the program enabling potential or the program inhibition potential.
摘要翻译：一种用于电可编程存储器的页面缓冲器，包括至少一个读/程序单元，其具有可操作地与至少一个所述位线相关联的耦合线，并且适于至少临时存储从或写入到存储在所选存储单元组的存储单元中的第一或第二存储器页。读/程序单元包括启用装置，用于通过使耦合线在程序使能电位和程序禁止电位之间采取一种方式来有选择地启用所选择的存储单元的编程状态的改变，所选存储单元的第一组数据位和已存储在所选存储单元的第二组数据位中的现有数据值。启用装置包括用于检索现有数据值的读取装置，用于接收目标数据值的指示的装置，用于将接收的目标数据值与所检索的现有数据值组合的组合装置，从而修改目标数据值的所述指示，从而以获得修改的指示。组合装置中的调节装置基于现有数据值和修改的指示来条件耦合线的电位，以使耦合线采取程序使能电位或程序禁止电位。

6. 发明申请

US20110167206A1 CONFIGURATION OF A MULTILEVEL FLASH MEMORY DEVICE 有权
标题翻译：多级闪存存储器件的配置
公开(公告)号：US20110167206A1
公开(公告)日：2011-07-07
申请号：US13048760
申请日：2011-03-15
申请人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
发明人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F12/02
CPC分类号： G11C11/5621 , G11C16/20
摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
摘要翻译：多级闪存设备允许更快更有效地配置存储器设备的操作参数，以执行存储器的不同功能的算法。在测试期间识别存储器件的操作参数的最佳配置通过允许将配置位一次性处理成算法友好的数据来简化，该数据存储在嵌入式辅助随机存取存储器中，每次上电时存储设备。这通过执行存储在嵌入式微处理器的辅助只读存储器中的特定加电算法代码来完成。

7. 发明申请

US20070030730A1 Nand flash memory with erase verify based on shorter evaluation time 有权
标题翻译：基于更短的评估时间，具有擦除验证的Nand闪存
公开(公告)号：US20070030730A1
公开(公告)日：2007-02-08
申请号：US11495886
申请日：2006-07-28
申请人： Angelo Bovino , Rino Micheloni , Roberto Ravasio
发明人： Angelo Bovino , Rino Micheloni , Roberto Ravasio
IPC分类号： G11C16/06
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C2211/5621 , G11C2211/5642 , G11C2216/14
摘要： A non-volatile memory device is proposed. The non-volatile memory device includes a plurality of memory cells each one having a programmable threshold voltage, and means for reading a set of selected memory cells with respect to a plurality of reference voltages, for each selected memory cell the means for reading including means for charging a reading node associated with the selected memory cell with a charging voltage, means for biasing the selected memory cell with a biasing voltage, means for connecting the charged reading node with the biased selected memory cell, and means for sensing a voltage at the reading node after a predefined delay from the connection, for at least a first one of the reference voltages the biasing voltage being a first biasing voltage equal to the first reference voltage and the delay being a common first delay, wherein for at least a second one of the reference voltages the biasing voltage is a second biasing voltage different from the second reference voltage, and the delay is a second delay different from the first delay.
摘要翻译：提出了一种非易失性存储器件。该非易失性存储器件包括多个具有可编程阈值电压的存储单元，以及用于针对每个所选择的存储器单元读取相对于多个参考电压的一组所选存储单元的装置，所述读取装置包括装置用于利用充电电压对与所选择的存储器单元相关联的读取节点进行充电，用于利用偏置电压偏置所选择的存储单元的装置，用于将所述充电的读取节点与所偏置的选择的存储单元相连接的装置，以及用于感测所述存储单元在来自所述连接的预定义延迟之后的读取节点，对于所述参考电压中的至少第一参考电压，所述偏置电压是等于所述第一参考电压的第一偏置电压，并且所述延迟是公共的第一延迟，其中对于至少第二个的参考电压，偏置电压是与第二参考电压不同的第二偏置电压，并且延迟是第二延迟di 与第一次延迟不同。

8. 发明授权

US08572361B2 Configuration of a multilevel flash memory device 有权
标题翻译：配置多级闪存设备
公开(公告)号：US08572361B2
公开(公告)日：2013-10-29
申请号：US13048760
申请日：2011-03-15
申请人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
发明人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F9/24
CPC分类号： G11C11/5621 , G11C16/20
摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
摘要翻译：多级闪存设备允许更快更有效地配置存储器设备的操作参数，以执行存储器的不同功能的算法。在测试期间识别存储器件的操作参数的最佳配置通过允许将配置位一次性处理成算法友好的数据来简化，该数据存储在嵌入式辅助随机存取存储器中，每次上电时存储设备。这通过执行存储在嵌入式微处理器的辅助只读存储器中的特定加电算法代码来完成。

9. 发明授权

US07937576B2 Configuration of a multi-level flash memory device 有权
标题翻译：配置多级闪存设备
公开(公告)号：US07937576B2
公开(公告)日：2011-05-03
申请号：US11460777
申请日：2006-07-28
申请人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
发明人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F9/24
CPC分类号： G11C11/5621 , G11C16/20
摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
摘要翻译：多级闪存设备允许更快更有效地配置存储器设备的操作参数，以便执行存储器的不同功能算法。简化了测试过程中存储器件工作参数的最佳配置的识别通过在存储器件的每次上电时允许将配置位一次性处理成存储在嵌入式辅助随机存取存储器中的算法友好数据。这通过执行存储在存储器装置中的特定加电算法代码来完成嵌入式微处理器的辅助只读存储器。

10. 发明申请

US20070038852A1 CONFIGURATION OF A MULTILEVEL FLASH MEMORY DEVICE 有权
标题翻译：多个FLASH存储器件的配置
公开(公告)号：US20070038852A1
公开(公告)日：2007-02-15
申请号：US11460777
申请日：2006-07-28
申请人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
发明人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F15/177 , G06F9/24 , G06F9/00 , G11C16/04 , G11C11/34
CPC分类号： G11C11/5621 , G11C16/20
摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
摘要翻译：多级闪存设备允许更快更有效地配置存储器设备的操作参数，以执行存储器的不同功能算法。简化了测试过程中存储器件工作参数的最佳配置的识别通过在存储器件的每次上电时允许将配置位一次性处理成存储在嵌入式辅助随机存取存储器中的算法友好数据。这通过执行存储在存储器装置中的特定加电算法代码来完成嵌入式微处理器的辅助只读存储器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式