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1. 发明申请

US20060249836A1 Chip-scale package 有权
公开(公告)号：US20060249836A1
公开(公告)日：2006-11-09
申请号：US11409298
申请日：2006-04-21
申请人： Andy Farlow , Mark Pavier , Andrew Sawle , George Pearson , Martin Standing
发明人： Andy Farlow , Mark Pavier , Andrew Sawle , George Pearson , Martin Standing
IPC分类号： H01L23/34
CPC分类号： H01L24/33 , H01L23/041 , H01L23/492 , H01L24/27 , H01L24/29 , H01L24/83 , H01L2224/29 , H01L2224/29007 , H01L2224/291 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29311 , H01L2224/29347 , H01L2224/29355 , H01L2224/32245 , H01L2224/73153 , H01L2224/83801 , H01L2924/00013 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/0781 , H01L2924/13091 , H01L2924/15747 , H01L2924/16152 , H01L2924/166 , H01L2924/30105 , H01L2924/01083 , H01L2924/00014 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299
摘要： A semiconductor package including a conductive clip preferably in the shape of a can, a semiconductor die, and a conductive stack interposed between the die and the interior of the can which includes a conductive platform and a conductive adhesive body.

2. 发明授权

US08466546B2 Chip-scale package 有权
标题翻译：芯片级封装
公开(公告)号：US08466546B2
公开(公告)日：2013-06-18
申请号：US11409298
申请日：2006-04-21
申请人： Andy Farlow , Mark Pavier , Andrew N. Sawle , George Pearson , Martin Standing
发明人： Andy Farlow , Mark Pavier , Andrew N. Sawle , George Pearson , Martin Standing
IPC分类号： H01L23/48
CPC分类号： H01L24/33 , H01L23/041 , H01L23/492 , H01L24/27 , H01L24/29 , H01L24/83 , H01L2224/29 , H01L2224/29007 , H01L2224/291 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29311 , H01L2224/29347 , H01L2224/29355 , H01L2224/32245 , H01L2224/73153 , H01L2224/83801 , H01L2924/00013 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/0781 , H01L2924/13091 , H01L2924/15747 , H01L2924/16152 , H01L2924/166 , H01L2924/30105 , H01L2924/01083 , H01L2924/00014 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299
摘要： A semiconductor package including a conductive clip preferably in the shape of a can, a semiconductor die, and a conductive stack interposed between the die and the interior of the can which includes a conductive platform and a conductive adhesive body.
摘要翻译：一种半导体封装，其包括优选为罐形状的导电夹子，半导体管芯和插入在所述管芯和所述罐体内部的导电堆叠，其包括导电平台和导电粘合体。

3. 发明申请

US20070108585A1 Semiconductor package including a semiconductor die having redistributed pads 有权
标题翻译：半导体封装包括具有再分布焊盘的半导体管芯
公开(公告)号：US20070108585A1
公开(公告)日：2007-05-17
申请号：US11595206
申请日：2006-11-10
申请人： Mark Pavier , Andrew Sawle , Martin Standing
发明人： Mark Pavier , Andrew Sawle , Martin Standing
IPC分类号： H01L23/48
CPC分类号： H01L23/043 , H01L21/56 , H01L23/142 , H01L23/3128 , H01L23/3171 , H01L23/3675 , H01L23/3736 , H01L23/4334 , H01L23/492 , H01L23/49562 , H01L23/49582 , H01L23/49838 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/19 , H01L24/24 , H01L24/32 , H01L24/37 , H01L24/83 , H01L24/97 , H01L25/07 , H01L2224/0346 , H01L2224/0508 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/24226 , H01L2224/24227 , H01L2224/2919 , H01L2224/32245 , H01L2224/32257 , H01L2224/33181 , H01L2224/37147 , H01L2224/73153 , H01L2224/73267 , H01L2224/83815 , H01L2224/92244 , H01L2224/97 , H01L2924/0102 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0106 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/13055 , H01L2924/13091 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15738 , H01L2924/15747 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/40252 , H01L2924/403 , H01L2924/40407 , H01L2224/82 , H01L2224/83
摘要： A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.
摘要翻译：一种半导体封装，其包括半导体管芯，管芯周围的绝缘体，以及耦合到管芯的电极的一致的导电焊盘。

4. 发明授权

US07402507B2 Semiconductor package fabrication 有权
标题翻译：半导体封装制造
公开(公告)号：US07402507B2
公开(公告)日：2008-07-22
申请号：US11367725
申请日：2006-03-03
申请人： Martin Standing , Mark Pavier , Robert J. Clarke , Andrew Sawle , Kenneth McCartney
发明人： Martin Standing , Mark Pavier , Robert J. Clarke , Andrew Sawle , Kenneth McCartney
IPC分类号： H01L21/20
CPC分类号： H01L21/4825 , H01L21/4867 , H01L23/544 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/27 , H01L24/29 , H01L24/33 , H01L24/40 , H01L24/743 , H01L24/83 , H01L25/16 , H01L25/50 , H01L2223/54433 , H01L2223/54486 , H01L2224/0401 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/13099 , H01L2224/16 , H01L2224/274 , H01L2224/29 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/743 , H01L2224/83192 , H01L2224/83194 , H01L2224/838 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/1033 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/157 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H05K1/0266 , H05K3/1241 , H05K3/245 , H01L2924/00 , H01L2924/00014 , H01L2224/29099
摘要： A semiconductor package fabrication method in which drop on demand deposition of a drop on demand depositable material is used to prepare one component or a plurality of components of a semiconductor package or multi-chip module.
摘要翻译：一种半导体封装制造方法，其中使用按需存放材料的按需投入沉积来制备半导体封装或多芯片模块的一个组件或多个组件。

5. 发明申请

US20060205112A1 Semiconductor package fabrication 有权
标题翻译：半导体封装制造
公开(公告)号：US20060205112A1
公开(公告)日：2006-09-14
申请号：US11367725
申请日：2006-03-03
申请人： Martin Standing , Mark Pavier , Robert Clarke , Andrew Sawle , Kenneth McCartney
发明人： Martin Standing , Mark Pavier , Robert Clarke , Andrew Sawle , Kenneth McCartney
IPC分类号： H01L21/00
CPC分类号： H01L21/4825 , H01L21/4867 , H01L23/544 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/27 , H01L24/29 , H01L24/33 , H01L24/40 , H01L24/743 , H01L24/83 , H01L25/16 , H01L25/50 , H01L2223/54433 , H01L2223/54486 , H01L2224/0401 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/13099 , H01L2224/16 , H01L2224/274 , H01L2224/29 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/743 , H01L2224/83192 , H01L2224/83194 , H01L2224/838 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/1033 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/157 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H05K1/0266 , H05K3/1241 , H05K3/245 , H01L2924/00 , H01L2924/00014 , H01L2224/29099
摘要： A semiconductor package fabrication method in which drop on demand deposition of a drop on demand depositable material is used to prepare one component or a plurality of components of a semiconductor package or multi-chip module.
摘要翻译：一种半导体封装制造方法，其中使用按需存放材料的按需投入沉积来制备半导体封装或多芯片模块的一个组件或多个组件。

6. 发明申请

US20050269677A1 Preparation of front contact for surface mounting 审中-公开
标题翻译：表面安装前接触准备
公开(公告)号：US20050269677A1
公开(公告)日：2005-12-08
申请号：US11138141
申请日：2005-05-26
申请人： Martin Standing , Andrew Sawle , David Jones , Martin Carroll , Matthew Elwin
发明人： Martin Standing , Andrew Sawle , David Jones , Martin Carroll , Matthew Elwin
IPC分类号： H01L23/02 , H01L23/485 , H01L23/492
CPC分类号： H01L24/10 , H01L23/3171 , H01L23/492 , H01L24/13 , H01L2224/05573 , H01L2224/05624 , H01L2224/13 , H01L2224/13099 , H01L2224/73153 , H01L2224/73253 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device which includes a power electrode on a surface thereof, a solderable body on the power electrode and a passivation body spaced from but surrounding the solderable body.
摘要翻译：一种半导体器件，包括其表面上的功率电极，在所述电源电极上的可焊接体，以及与所述可焊接体相隔开但包围的钝化体。

7. 发明申请

US20050224960A1 Surface mounted package with die bottom spaced from support board 有权
公开(公告)号：US20050224960A1
公开(公告)日：2005-10-13
申请号：US11146628
申请日：2005-06-07
申请人： Martin Standing , Andrew Sawle
发明人： Martin Standing , Andrew Sawle
IPC分类号： H01L23/04 , H01L23/047 , H01L23/13 , H01L23/31 , H01L23/34 , H01L23/492
CPC分类号： H01L23/047 , H01L23/13 , H01L23/3114 , H01L23/492 , H01L24/37 , H01L2224/06181 , H01L2224/32245 , H01L2224/37147 , H01L2224/73153 , H01L2224/73253 , H01L2224/83801 , H01L2224/8385 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor package according to the present invention includes a metal can which receives in its interior space a MOSFET. The MOSFET so received is oriented such that its drain electrode is facing the bottom of the can and is electrically connected to the same by a layer of conductive epoxy or a solder or the like. The edges of the MOSFET so placed are spaced from the walls of the can. The space between the edges of the MOSFET and the walls of the can is filled with an insulating layer. A surface of the MOSFET is sub-flush below the plane of a substrate by 0.001-0.005 inches to reduce temperature cycling failures.

8. 发明授权

US08368211B2 Solderable top metalization and passivation for source mounted package 有权
标题翻译：可焊顶级金属化和源极安装封装的钝化
公开(公告)号：US08368211B2
公开(公告)日：2013-02-05
申请号：US10982965
申请日：2004-11-05
申请人： Martin Standing , Andrew Sawle , Matthew P Elwin , David P Jones , Martin Carroll , Ian Glenville Wagstaffe
发明人： Martin Standing , Andrew Sawle , Matthew P Elwin , David P Jones , Martin Carroll , Ian Glenville Wagstaffe
IPC分类号： H01L27/095
CPC分类号： H01L21/76829 , H01L23/3171 , H01L23/498 , H01L24/05 , H01L24/81 , H01L24/83 , H01L2224/0401 , H01L2224/05082 , H01L2224/05155 , H01L2224/05166 , H01L2224/05568 , H01L2224/05572 , H01L2224/05573 , H01L2224/05639 , H01L2224/81801 , H01L2224/83801 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01047 , H01L2924/01077 , H01L2924/014 , H01L2924/10253 , H01L2924/10272 , H01L2924/1033 , H01L2924/1306 , H01L2924/13091 , H01L2924/00 , H01L2224/05552
摘要： A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.
摘要翻译：在半导体管芯上的含银可焊接触点具有与环氧钝化层的相对边缘隔开的外边缘，使得在焊接之后，不存在银离子，并且不会在环氧树脂层下自由迁移以形成枝晶。

9. 发明申请

US20070091546A1 UNIVERSAL PAD ARRANGEMENT FOR SURFACE MOUNTED SEMICONDUCTOR DEVICES 有权
标题翻译：表面安装半导体器件的通用焊盘布置
公开(公告)号：US20070091546A1
公开(公告)日：2007-04-26
申请号：US11551767
申请日：2006-10-23
申请人： Martin Standing , Andrew Sawle
发明人： Martin Standing , Andrew Sawle
IPC分类号： H02B1/00
CPC分类号： H05K1/111 , H01L2924/0002 , H05K1/0295 , H05K2201/09954 , H05K2201/10166 , Y02P70/611 , H01L2924/00
摘要： An apparatus for coupling a plurality of surface mounted semiconductor device packages to a circuit board is provided. Each package including a semiconductor device die and a metal clip including a flat web portion having a bottom surface and at least one peripheral rim portion extending from an edge of said flat web portion, said bottom surface having solderable planar metal electrodes or pads on its bottom surface, the contact pads being formed in plurality of layouts having one or more columns and one or more rows. The apparatus including a circuit board contact pattern including one or more columns and one or more rows of contacts, a number of rows being equal to a largest number of contact pad rows in the plurality of contact pad layouts, a number of columns being equal to a largest number of contact pad columns in the plurality of contact pad layouts. The circuit board contact pattern is usable by all of the plurality of the contact pad layouts of the plurality of semiconductor device packages.
摘要翻译：提供了一种用于将多个表面安装的半导体器件封装耦合到电路板的装置。每个包装包括半导体器件芯片和金属夹子，其包括具有底表面的平坦腹板部分和从所述扁平腹板部分的边缘延伸的至少一个周边边缘部分，所述底部表面具有可焊接的平面金属电极或其底部的焊盘表面，接触垫形成为具有一个或多个列和一行或多行的多个布局。该装置包括包括一个或多个列和一行或多行触点的电路板触点图案，多个行等于多个接触焊盘布局中的最大数量的接触焊盘行，多个列等于多个接触垫布局中的最大数量的接触垫列。电路板接触图案可由多个半导体器件封装的多个接触焊盘布局中的全部可用。

10. 发明申请

US20070052099A1 Protective barrier layer for semiconductor device electrodes 有权
标题翻译：半导体器件电极用保护层
公开(公告)号：US20070052099A1
公开(公告)日：2007-03-08
申请号：US11515652
申请日：2006-09-05
申请人： Martin Carroll , David Jones , Andrew Sawle , Martin Standing
发明人： Martin Carroll , David Jones , Andrew Sawle , Martin Standing
IPC分类号： H01L23/52
CPC分类号： H01L23/485 , H01L21/76846 , H01L21/76852 , H01L21/76865 , H01L21/76897 , H01L23/3157 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05022 , H01L2224/05557 , H01L2224/05558 , H01L2224/0558 , H01L2224/05624 , H01L2224/05639 , H01L2224/114 , H01L2224/116 , H01L2224/13006 , H01L2224/13021 , H01L2224/85424 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01074 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/1306 , H01L2924/13091 , H01L2924/3025 , H01L2224/13099 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor device includes a die with at least one electrode on a surface thereof, at least one solderable contact formed on the electrode, and a passivation layer formed over the electrode and including an opening that exposes the solderable contact. The passivation layer opening may be wider than the solderable contact such that a gap extends between the contact and the passivation layer. The device also includes a barrier layer disposed on the top surface of the electrode, and along the underside of the solderable contact and across the gap. The barrier layer may also extend under the passivation layer and may cover the entire top surface of the electrode. The barrier layer may also extend along the sidewalls of the electrode. The barrier layer may include a titanium layer or a titanium layer and nickel layer. The barrier layer protects the electrode and underlying die from acidic fluxes found in lead-free solders.
摘要翻译：半导体器件包括具有在其表面上的至少一个电极的模具，形成在电极上的至少一个可焊接触头，以及形成在电极上并包括暴露可焊接触点的开口的钝化层。钝化层开口可以比可焊接触点宽，使得间隙在触点和钝化层之间延伸。该装置还包括设置在电极的顶表面上并沿着可焊接触点的下侧并跨越间隙的阻挡层。阻挡层还可以在钝化层下方延伸并且可以覆盖电极的整个顶表面。阻挡层也可以沿着电极的侧壁延伸。阻挡层可以包括钛层或钛层和镍层。阻挡层保护电极和底层管芯免受在无铅焊料中发现的酸性焊剂的影响。

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