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1. 发明授权

US06763034B1 Connection ports for interconnecting modules in an integrated circuit 有权
标题翻译：用于在集成电路中互连模块的连接端口
公开(公告)号：US06763034B1
公开(公告)日：2004-07-13
申请号：US09411828
申请日：1999-10-01
申请人： Andrew M. Jones , John A. Carey , Atsushi Hasegawa
发明人： Andrew M. Jones , John A. Carey , Atsushi Hasegawa
IPC分类号： H04L1266
CPC分类号： H04L49/102 , G06F15/7825 , H04L49/555
摘要： Connection ports for interconnecting functional modules in an integrated circuit are described. The connection ports provide enhanced functionality based around a common port primitive. This simplifies port design and selection and also allows a common packet protocol to be used for communication of packets across the packet router. In particular, there is improved functionality of target ports which allow out of order requests to be dealt with and out of order responses to be generated.
摘要翻译：描述用于在集成电路中互连功能模块的连接端口。连接端口基于公共端口原语提供增强的功能。这简化了端口设计和选择，并且还允许通用分组协议用于通过分组路由器的分组通信。特别地，改进了目标端口的功能，这些端口允许处理不及时的请求并产生无序响应。

2. 发明授权

US06590907B1 Integrated circuit with additional ports 有权
标题翻译：集成电路与附加端口
公开(公告)号：US06590907B1
公开(公告)日：2003-07-08
申请号：US09411799
申请日：1999-10-01
申请人： Andrew M. Jones , John A. Carey , Bernard Ramanadin , Atsushi Hasegawa
发明人： Andrew M. Jones , John A. Carey , Bernard Ramanadin , Atsushi Hasegawa
IPC分类号： G06F1300
CPC分类号： H04L45/60 , G06F13/364 , G06F13/4022 , H04L45/00 , H04L49/45
摘要： An integrated circuit which has a packet router to which a plurality of functional modules are connected by respective ports is described. One of the ports acts as a socket port for an expansion socket. The expansion socket provides a plurality of additional expansion ports to which additional functional modules can optionally be connected. All the ports connected to the packet router, including the expansion socket port, preferably lie in a common address space for the integrated circuit.
摘要翻译：描述了具有通过各个端口连接多个功能模块的分组路由器的集成电路。其中一个端口用作扩展插座的插座端口。扩展插座提供多个额外的扩展端口，附加的功能模块可以可选地连接到该扩展端口。连接到分组路由器的所有端口，包括扩展插座端口，优选地位于集成电路的公共地址空间中。

3. 发明授权

US07796624B2 Systems and methods for providing single-packet and multi-packet transactions in an integrated circuit 有权
标题翻译：用于在集成电路中提供单分组和多分组事务的系统和方法
公开(公告)号：US07796624B2
公开(公告)日：2010-09-14
申请号：US10819552
申请日：2004-04-07
申请人： Andrew M. Jones , John A. Carey , Atsushi Hasegawa
发明人： Andrew M. Jones , John A. Carey , Atsushi Hasegawa
IPC分类号： H04L12/28
CPC分类号： H04L49/102 , G06F15/7825 , H04L49/555
摘要： Connection ports for interconnecting functional modules in an integrated circuit are described. The connection ports provide enhanced functionality based around a common port primitive. This simplifies port design and selection and also allows a common packet protocol to be used for communication of packets across the packet router. In particular, there is improved functionality of target ports which allow out of order requests to be dealt with and out of order responses to be generated.
摘要翻译：描述用于在集成电路中互连功能模块的连接端口。连接端口基于公共端口原语提供增强的功能。这简化了端口设计和选择，并且还允许公共分组协议用于通过分组路由器的分组通信。特别地，改进了目标端口的功能，这些端口允许处理不及时的请求并产生无序响应。

4. 发明授权

US07346072B2 Arbitration mechanism for packet transmission 有权
标题翻译：分组传输的仲裁机制
公开(公告)号：US07346072B2
公开(公告)日：2008-03-18
申请号：US10780355
申请日：2004-02-17
申请人： Andrew M. Jones , John A. Carey
发明人： Andrew M. Jones , John A. Carey
IPC分类号： H04L12/43
CPC分类号： H04L45/00
摘要： A pipelined arbitration mechanism allows a routing control decision to be effected for a later packet while a current packet is being transferred. The later packet can be issued a fixed number of cycles after the current request. The mechanism has particular advantages when used with a plurality of functional modules connected to a packet router, whereby a single functional module can generate a current request relating to a current packet and a deferred arbitration request relating to a later packet to be issued a fixed number of cycles after the current request.
摘要翻译：流水线仲裁机制允许在当前分组正在传输时对稍后的分组进行路由控制决定。稍后的数据包可以在当前请求之后发出固定数量的周期。当与连接到分组路由器的多个功能模块一起使用时，该机制具有特别的优点，由此单个功能模块可以生成与当前分组有关的当前请求以及与要发布固定数量的稍后分组有关的延迟仲裁请求的当前请求后的周期。

5. 发明授权

US07266728B1 Circuit for monitoring information on an interconnect 有权
标题翻译：用于监控互连信息的电路
公开(公告)号：US07266728B1
公开(公告)日：2007-09-04
申请号：US09410646
申请日：1999-10-01
申请人： David A. Edwards , Andrew M. Jones , John A. Carey , Anthony W. Rich
发明人： David A. Edwards , Andrew M. Jones , John A. Carey , Anthony W. Rich
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/364 , G06F11/3648
摘要： A circuit for monitoring information put onto an interconnect by one or more modules, said circuit comprising circuitry for determining if the information on the interconnect matches one or more conditions; and circuitry for preventing a module from putting further information onto said interconnect if it is determined that information on the interconnect matches said one or more conditions.
摘要翻译：一种用于监视由一个或多个模块放在互连上的信息的电路，所述电路包括用于确定所述互连上的信息是否匹配一个或多个条件的电路; 以及用于如果确定互连上的信息匹配所述一个或多个条件，则用于防止模块将更多信息放入所述互连的电路。

6. 发明授权

US06349371B1 Circuit for storing information 有权
标题翻译：用于存储信息的电路
公开(公告)号：US06349371B1
公开(公告)日：2002-02-19
申请号：US09411800
申请日：1999-10-01
申请人： Bernard Ramanadin , David A. Edwards , Andrew M. Jones , John A. Carey , Anthony W. Rich
发明人： Bernard Ramanadin , David A. Edwards , Andrew M. Jones , John A. Carey , Anthony W. Rich
IPC分类号： G06F1200
CPC分类号： G06F11/364 , G06F11/3485
摘要： In a system comprising an interconnect and a plurality of modules connected to the interconnect, a circuit for controlling which of said modules is able to put information onto said interconnect, said circuit comprising a store which stores status information for each module, said status information defining if the respective module is permitted to put information on said interconnect.
摘要翻译：在包括连接到互连的互连和多个模块的系统中，用于控制所述模块中的哪一个能够将信息放置在所述互连上的电路，所述电路包括存储每个模块的状态信息的存储器，所述状态信息定义如果允许相应的模块将信息放在所述互连上。

7. 发明授权

US06826191B1 Packets containing transaction attributes 有权
标题翻译：包含事务属性的数据包
公开(公告)号：US06826191B1
公开(公告)日：2004-11-30
申请号：US09411419
申请日：1999-10-01
申请人： Andrew M. Jones , John A. Carey
发明人： Andrew M. Jones , John A. Carey
IPC分类号： H04L1228
CPC分类号： G06F13/14
摘要： An integrated circuit comprising a plurality of functional modules and interconnected via a packet router for conveying request and response packets is described. Transactions involve the dispatch of request packets and receipt of corresponding response packets. Each packet conveys a number of transaction attributes which can control how the packet is managed by control circuitry which controls the flow of packets on the packet router. For example the transaction attributes can include a transaction number, a grouping indicator, a priority indicator and a post indicator.
摘要翻译：描述了包括多个功能模块并经由用于传送请求和响应分组的分组路由器互连的集成电路。交易涉及发送请求报文和收到相应的响应报文。每个分组传送多个事务属性，其可以控制分组如何由控制电路管理，该控制电路控制分组路由器上的分组流。例如，事务属性可以包括事务号，分组指示符，优先级指示符和后置指示符。

8. 发明授权

US06928073B2 Integrated circuit implementing packet transmission 有权
标题翻译：集成电路实现分组传输
公开(公告)号：US06928073B2
公开(公告)日：2005-08-09
申请号：US09410974
申请日：1999-10-01
申请人： Andrew M. Jones , John A. Carey
发明人： Andrew M. Jones , John A. Carey
IPC分类号： G06F9/312 , G06F9/315 , H04L12/56
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043
摘要： The implementation of transactions on an integrated circuit comprising a plurality of functional modules connected to a packet router is described. Each functional module generates request packets for implementing memory access operations, each request packet having an operation field comprising eight bits of which a packet type bit denotes the type of the packet, four operation family bit denote the function to be implemented by the packet and three operation qualifier bits act to qualify the function.
摘要翻译：描述了在包括连接到分组路由器的多个功能模块的集成电路上的事务的实现。每个功能模块生成用于实现存储器访问操作的请求分组，每个请求分组具有包括八位的操作字段，其中分组类型位表示分组的类型，四个操作系列表示要由分组实现的功能，三个操作限定符位用于限定功能。

9. 发明授权

US06693914B1 Arbitration mechanism for packet transmission 有权
标题翻译：分组传输的仲裁机制
公开(公告)号：US06693914B1
公开(公告)日：2004-02-17
申请号：US09411429
申请日：1999-10-01
申请人： Andrew M. Jones , John A. Carey
发明人： Andrew M. Jones , John A. Carey
IPC分类号： H04L1243
CPC分类号： H04L45/00
摘要： A pipelined arbitration mechanism allows a routing control decision to be effected for a later packet while a current packet is being transferred. The later packet can be issued a fixed number of cycles after the current request. The mechanism has particular advantages when used with a plurality of functional modules connected to a packet router, whereby a single functional module can generate a current request relating to a current packet and a deferred arbitration request relating to a later packet to be issued a fixed number of cycles after the current request.
摘要翻译：流水线仲裁机制允许在当前分组正在传输时对稍后的分组进行路由控制决定。稍后的数据包可以在当前请求之后发出固定数量的周期。当与连接到分组路由器的多个功能模块一起使用时，该机制具有特别的优点，由此单个功能模块可以生成与当前分组有关的当前请求以及与要发布固定数量的稍后分组有关的延迟仲裁请求的当前请求后的周期。

10. 发明授权

US07072817B1 Method of designing an initiator in an integrated circuit 有权
标题翻译：在集成电路中设计启动器的方法
公开(公告)号：US07072817B1
公开(公告)日：2006-07-04
申请号：US09411418
申请日：1999-10-01
申请人： John A. Carey
发明人： John A. Carey
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for designing an integrated circuit where the integrated circuit includes a plurality of modules and where each module includes an initiator port and a target port coupled to a distributed routing network. The initiator port is implemented by configuring whether the initiator or the distributed routing network is responsible for ordering responses to requests issued by the initiator port and defining the maximum number of requests that are permitted to be outstanding at the same time. The initiator port is further configured to define whether a delay stage is required in said initiator port. The distributed routing network is defined by the number of routing resources between the initiator and the target, an arbitration method for arbitrating between requests and an association between the routing resources and the targets.
摘要翻译：一种用于设计集成电路的方法，其中集成电路包括多个模块，并且其中每个模块包括耦合到分布式路由网络的发起者端口和目标端口。通过配置发起方或分布式路由网络是否负责对发起方端口发出的请求的响应进行排序并定义同时允许未完成的请求的最大数量来实现发起方端口。发起者端口还被配置为定义在所述发起者端口中是否需要延迟级。分布式路由网络由发起方和目标之间的路由资源数量定义，用于仲裁请求之间的仲裁方法和路由资源与目标之间的关联。

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