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1. 发明申请

US20190067028A1 VAPOR-ETCH CYCLIC PROCESS 审中-公开
公开(公告)号：US20190067028A1
公开(公告)日：2019-02-28
申请号：US15686526
申请日：2017-08-25
申请人： Andrew L. Li , Prashant Raghu , Sanjeev Sapra , Rita J. Klein , Sanh D. Tang , Sourabh Dhir
发明人： Andrew L. Li , Prashant Raghu , Sanjeev Sapra , Rita J. Klein , Sanh D. Tang , Sourabh Dhir
IPC分类号： H01L21/311 , H01L21/02 , H01L27/108 , H01L21/66 , H01L21/67
摘要： Various embodiments comprise methods of selectively etching oxides over nitrides in a vapor-etch cyclic process. In one embodiment, the method includes, in a first portion of the vapor-etch cyclic process, exposing a substrate having oxide features and nitride features formed thereon to selected etchants in a vapor-phase chamber; transferring the substrate to a post-etch heat treatment chamber; and heating the substrate to remove etchant reaction products from the substrate. In a second portion of the vapor-etch cyclic process, the method continues with transferring the substrate from the post-etch heat treatment chamber to the vapor-phase chamber; exposing the substrate to the selected etchants in the vapor-phase chamber; transferring the substrate to the post-etch heat treatment chamber; and heating the substrate to remove additional etchant reaction products from the substrate. Apparatuses for performing the method and additional methods are also disclosed.

2. 发明授权

US07659560B2 Transistor structures 有权
标题翻译：晶体管结构
公开(公告)号：US07659560B2
公开(公告)日：2010-02-09
申请号：US11716433
申请日：2007-03-08
申请人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L21/8238
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译：晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。填充层相对于金属层基本上可选择性地蚀刻。晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。本发明至少应用于三维晶体管结构。

3. 发明授权

US07867845B2 Transistor gate forming methods and transistor structures 有权
标题翻译：晶体管栅极形成方法和晶体管结构
公开(公告)号：US07867845B2
公开(公告)日：2011-01-11
申请号：US11219077
申请日：2005-09-01
申请人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L29/76
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译：晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。填充层相对于金属层基本上可选择性地蚀刻。晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。本发明至少应用于三维晶体管结构。

4. 发明申请

US20110092062A1 Transistor Gate Forming Methods and Transistor Structures 有权
标题翻译：晶体管栅极形成方法和晶体管结构
公开(公告)号：US20110092062A1
公开(公告)日：2011-04-21
申请号：US12977969
申请日：2010-12-23
申请人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L21/28
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译：晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。填充层相对于金属层基本上可选择性地蚀刻。晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。本发明至少应用于三维晶体管结构。

5. 发明授权

US08349687B2 Transistor gate forming methods and transistor structures 有权
标题翻译：晶体管栅极形成方法和晶体管结构
公开(公告)号：US08349687B2
公开(公告)日：2013-01-08
申请号：US12977969
申请日：2010-12-23
申请人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L29/76
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译：晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。填充层相对于金属层基本上可选择性地蚀刻。晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。本发明至少应用于三维晶体管结构。

6. 发明授权

US09012318B2 Etching polysilicon 有权
标题翻译：蚀刻多晶硅
公开(公告)号：US09012318B2
公开(公告)日：2015-04-21
申请号：US13624272
申请日：2012-09-21
申请人： Jerome A. Imonigie , Prashant Raghu
发明人： Jerome A. Imonigie , Prashant Raghu
IPC分类号： H01L21/336 , C09K13/08 , H01L21/28 , H01L21/3213 , H01L27/115
CPC分类号： C09K13/08 , C09K13/00 , C09K13/04 , C09K13/06 , H01L21/28273 , H01L21/30604 , H01L21/31111 , H01L21/32134 , H01L27/11556
摘要： Methods and compositions for etching polysilicon including aqueous compositions containing nitric acid and ammonium fluoride, and apparatus formed thereby.
摘要翻译：用于蚀刻多晶硅的方法和组合物，包括含有硝酸和氟化铵的含水组合物，以及由此形成的装置。

7. 发明授权

US08962460B2 Methods of selectively forming metal-doped chalcogenide materials, methods of selectively doping chalcogenide materials, and methods of forming semiconductor device structures including same 有权
标题翻译：选择性地形成金属掺杂的硫族化物材料的方法，选择性掺杂硫族化物材料的方法，以及形成包括它们的半导体器件结构的方法
公开(公告)号：US08962460B2
公开(公告)日：2015-02-24
申请号：US13094024
申请日：2011-04-26
申请人： Jerome A. Imonigie , Prashant Raghu , Theodore M. Taylor , Scott E. Sills
发明人： Jerome A. Imonigie , Prashant Raghu , Theodore M. Taylor , Scott E. Sills
IPC分类号： H01L21/22 , H01L21/38 , H01L45/00
CPC分类号： H01L45/1658 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1608 , H01L45/1641
摘要： Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide. Another method comprises forming a chalcogenide material adjacent to and in contact with an insulative material, exposing the chalcogenide material and the insulative material to a transition metal solution, and diffusing transition metal of the transition metal solution into the chalcogenide material while substantially no transition metal diffuses into the insulative material. A method of doping a chalcogenide material of a memory cell with at least one transition metal without using an etch or chemical mechanical planarization process to remove the transition metal from an insulative material of the memory cell is also disclosed, wherein the chalcogenide material is not silver selenide.
摘要翻译：选择性地形成金属掺杂的硫族化物材料的方法包括将硫族化物材料暴露于过渡金属溶液，并将过渡溶液的过渡金属掺入硫族化物材料中，而基本上不将过渡金属掺入相邻的材料中。硫族化物材料不是硒化银。另一种方法包括形成与绝缘材料相邻并与其接触的硫族化物材料，将硫属化物材料和绝缘材料暴露于过渡金属溶液，并将过渡金属溶液的过渡金属扩散到硫属化物材料中，同时基本上没有过渡金属扩散进入绝缘材料。还公开了一种使用至少一种过渡金属掺杂存储单元的硫族化物材料而不使用蚀刻或化学机械平坦化工艺以从存储器单元的绝缘材料除去过渡金属的方法，其中硫族化物材料不是银硒化物

8. 发明申请

US20140087551A1 ETCHING POLYSILICON 有权
标题翻译：蚀刻多晶硅
公开(公告)号：US20140087551A1
公开(公告)日：2014-03-27
申请号：US13624272
申请日：2012-09-21
申请人： Jerome A. IMONIGIE , Prashant Raghu
发明人： Jerome A. IMONIGIE , Prashant Raghu
IPC分类号： C09K13/08 , H01L21/336
CPC分类号： C09K13/08 , C09K13/00 , C09K13/04 , C09K13/06 , H01L21/28273 , H01L21/30604 , H01L21/31111 , H01L21/32134 , H01L27/11556
摘要： Methods and compositions for etching polysilicon including aqueous compositions containing nitric acid and ammonium fluoride, and apparatus formed thereby.
摘要翻译：用于蚀刻多晶硅的方法和组合物，包括含有硝酸和氟化铵的含水组合物，以及由此形成的装置。

9. 发明申请

US20130334594A1 RECESSED GATE MEMORY APPARATUSES AND METHODS 审中-公开
标题翻译：闭门器记忆装置和方法
公开(公告)号：US20130334594A1
公开(公告)日：2013-12-19
申请号：US13524803
申请日：2012-06-15
申请人： Jerome A. Imonigie , Patrick M. Flynn , Sandra L. Tagg , Prashant Raghu
发明人： Jerome A. Imonigie , Patrick M. Flynn , Sandra L. Tagg , Prashant Raghu
IPC分类号： H01L29/792 , H01L21/28 , H01L21/306
CPC分类号： H01L21/32135 , H01L21/32134 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： Some embodiments include a memory device and a method of forming the memory device. One such memory device includes a string of stacked memory cells. Each of the memory cells in the string includes a charge storage structure and a recessed control gate. The recessed control gate has a substantially smooth surface separated from the charge storage structure by dielectric material. One such method includes etching heavily boron doped polysilicon selective to oxide to form a recessed control gate having a surface with nubs. A smoothing solution is applied to the surface of the recessed control gate to smoothen the nubs. Additional apparatuses and methods are described.
摘要翻译：一些实施例包括存储器件和形成存储器件的方法。一个这样的存储器件包括一堆堆叠的存储器单元。串中的每个存储单元包括电荷存储结构和凹入控制门。凹陷的控制栅极具有通过介电材料与电荷存储结构分离的基本平滑的表面。一种这样的方法包括蚀刻对氧化物选择性的重硼掺杂多晶硅以形成具有带有凸块的表面的凹陷控制栅极。将平滑解决方案应用于凹入控制门的表面以平滑微调。描述附加的装置和方法。

10. 发明授权

US08273261B2 Methods of forming semiconductor constructions 失效
标题翻译：形成半导体结构的方法
公开(公告)号：US08273261B2
公开(公告)日：2012-09-25
申请号：US12750457
申请日：2010-03-30
申请人： Prashant Raghu
发明人： Prashant Raghu
IPC分类号： C03C15/00
CPC分类号： H01L21/30604 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed from between titanium-containing capacitor electrodes. Such removal can be, for example, accomplished with an etch utilizing one or more of hydrofluoric acid, ammonium fluoride, nitric acid and hydrogen peroxide.
摘要翻译：本发明包括使用其中含有含磷和氧的化合物的蚀刻组合物从含钛容器结构中除去硅的方法。蚀刻组合物可以例如包括氢氧化铵和四甲基氢氧化铵中的一种或两种。本发明还包括从含钛电容器电极之间除去含钛晶须的方法。这种去除可以例如通过使用氢氟酸，氟化铵，硝酸和过氧化氢中的一种或多种的蚀刻来实现。

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