专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07210023B2 Data processing apparatus and method for moving data between registers and memory in response to an access instruction having an alignment specifier identifying an alignment to be associated with a start address 有权
标题翻译：数据处理装置和方法，用于响应于具有标识与开始地址相关联的对准的对准指定符的访问指令来在寄存器和存储器之间移动数据
公开(公告)号：US07210023B2
公开(公告)日：2007-04-24
申请号：US10889470
申请日：2004-07-13
申请人： Andrew Christopher Rose , Simon Andrew Ford , Dominic Hugo Symes , David James Seal
发明人： Andrew Christopher Rose , Simon Andrew Ford , Dominic Hugo Symes , David James Seal
IPC分类号： G06F7/00
CPC分类号： G06F9/3004 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30116 , G06F9/30138 , G06F9/30181 , G06F9/3816
摘要： The present invention provides a data processing apparatus and method for performing aligned access operations. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements, and a processor operable to perform a data processing operation on one or more data elements accessed in at least one of the registers. Further, access logic is provided which is operable in response to an access instruction to perform an access operation in order to move a number of data elements between specified registers and a portion of a memory, the portion having a start address specified by the access instruction. Further, the access instruction has an alignment specifier associated therewith which is settable either to a first value or one of a plurality of second values. The first value indicates that the start address is to be treated as byte aligned, and each of the second values indicates a different predetermined alignment that the start address is to be treated as conforming to. The access logic is then operable to adapt the access operation in dependence on the value of alignment specifier. This provides significantly improved flexibility in the performance of access operations.
摘要翻译：本发明提供一种用于执行对准访问操作的数据处理装置和方法。数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器，以及可操作以对在至少一个寄存器中访问的一个或多个数据元素执行数据处理操作的处理器。此外，提供访问逻辑，其可响应于访问指令而操作以执行访问操作，以便在指定的寄存器和存储器的一部分之间移动多个数据元素，该部分具有由访问指令指定的起始地址。此外，访问指令具有与其相关联的对齐说明符，其可设置为第一值或多个第二值中的一个。第一个值表示起始地址被视为字节对齐，并且每个第二个值指示起始地址被视为符合的不同的预定对齐方式。然后，访问逻辑可操作以根据对准说明符的值来适应访问操作。这样可以显着提高访问操作性能的灵活性。

2. 发明授权

US07219214B2 Data processing apparatus and method for moving data elements between a chosen lane of parallel processing in registers and a structure within memory 有权
标题翻译：用于在所选择的寄存器并行处理通道和存储器内的结构之间移动数据元素的数据处理装置和方法
公开(公告)号：US07219214B2
公开(公告)日：2007-05-15
申请号：US10889318
申请日：2004-07-13
申请人： Simon Andrew Ford , Dominic Hugo Symes , Andrew Christopher Rose , David Raymond Lutz , Christopher Neal Hinds
发明人： Simon Andrew Ford , Dominic Hugo Symes , Andrew Christopher Rose , David Raymond Lutz , Christopher Neal Hinds
IPC分类号： G06F9/00 , G06F9/44
CPC分类号： G06F9/3887 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30109 , G06F9/30112 , G06F9/30138 , G06F9/3822 , G06F9/3885
摘要： A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements occupying different lanes of parallel processing in at least one of the registers. Access logic is provided which is responsive to a single access instruction to move a plurality of data elements between a chosen one of the lanes in specified registers and a structure within memory having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is operation to arrange the plurality of data elements as they are moved such that data elements of different components are stored in different specified registers within the chosen lane whilst in memory the data elements are stored as the structure.
摘要翻译：提供了一种用于在寄存器和存储器之间移动数据的数据处理装置和方法。数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器。处理器可操作以并行地执行对至少一个寄存器中的并行处理的不同通道的多个数据元素的数据处理操作。提供了访问逻辑，其响应于单个访问指令，以在指定寄存器中的所选择的一个通道中移动多个数据元素，以及在具有结构格式的存储器内的结构，所述结构格式具有多个组件。单个访问指令标识结构格式中的组件的数量，并且访问逻辑是在移动多个数据元素时排列多个数据元素的操作，使得不同组件的数据元素存储在所选择的通道内的不同指定的寄存器中，同时存储数据元素作为结构存储。

3. 发明授权

US07219215B2 Data processing apparatus and method for moving data elements between specified registers and a continuous block of memory 有权
标题翻译：用于在指定的寄存器和连续的存储器块之间移动数据元素的数据处理装置和方法
公开(公告)号：US07219215B2
公开(公告)日：2007-05-15
申请号：US10889367
申请日：2004-07-13
申请人： Simon Andrew Ford , Dominic Hugo Symes , Andrew Christopher Rose , David Raymond Lutz , Christopher Neal Hinds
发明人： Simon Andrew Ford , Dominic Hugo Symes , Andrew Christopher Rose , David Raymond Lutz , Christopher Neal Hinds
IPC分类号： G06F9/40
CPC分类号： G06F9/30167 , G06F9/30025 , G06F9/30036 , G06F9/3004 , G06F9/30145
摘要： A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements accessed in at least one of the registers. Access logic is operable in response to a single access instruction to move a plurality of data elements between specified registers and a continuous block of memory in which data elements are stored as an array of structures having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is further operable to rearrange the plurality of data elements as they are moved such that each specified register stores data elements of one component whilst in memory the data elements are stored as the array of structures.
摘要翻译：提供了一种用于在寄存器和存储器之间移动数据的数据处理装置和方法。数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器。处理器可操作以对在至少一个寄存器中访问的多个数据元素并行地执行数据处理操作。访问逻辑可操作以响应于单个访问指令来移动指定寄存器之间的多个数据元素和其中数据元素被存储为具有结构格式的结构的阵列的连续存储块，所述结构格式具有多个组件。单个访问指令标识结构格式的组件的数量，并且访问逻辑还可用于在移动多个数据元素时重新排列多个数据元素，使得每个指定的寄存器存储一个组件的数据元素，而在存储器中数据元素是存储为结构数组。

4. 发明授权

US09557994B2 Data processing apparatus and method for performing N-way interleaving and de-interleaving operations where N is an odd plural number 有权
标题翻译：数据处理装置和方法，用于执行N为奇数的N次交织和解交织操作
公开(公告)号：US09557994B2
公开(公告)日：2017-01-31
申请号：US12588412
申请日：2009-10-14
申请人： Dominic Hugo Symes , Simon Andrew Ford
发明人： Dominic Hugo Symes , Simon Andrew Ford
IPC分类号： G06F9/30 , G06F9/345 , G06F9/38 , G06F7/48
CPC分类号： G06F9/30021 , G06F7/4812 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/30138 , G06F9/3016 , G06F9/30167 , G06F9/30189 , G06F9/345 , G06F9/382 , G06F9/3832 , G06F9/3873 , G06F9/3887 , G06F2207/3828
摘要： A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements. An instruction decoder is responsive to at least one but no more than N rearrangement instructions, where N is an odd plural number, to generate control signals to control the processing circuitry to perform a rearrangement process at least equivalent to: obtaining as source data elements the data elements stored in N registers of said register data store as identified by the at least one re-arrangement instruction; performing a rearrangement operation to rearrange the source data elements between a regular N-way interleaved order and a de-interleaved order in order to produce a sequence of result data elements; and outputting the sequence of result data elements for storing in the register data store. This provides a particularly efficient technique for performing N-way interleave and de-interleave operations, where N is an odd number, resulting in high performance, low energy consumption, and reduced register use when compared with known prior art techniques.
摘要翻译：提供了一种执行重排操作的数据处理装置和方法。数据处理装置具有具有多个寄存器的寄存器数据存储器，每个寄存器存储多个数据元素。处理电路响应于控制信号来对数据元素执行处理操作。指令解码器响应于至少一个但不超过N个重排指令，其中N是奇数复数，以产生控制信号，以控制处理电路执行至少等同于：作为源数据元素的重新排列过程存储在由所述至少一个重新布置指令识别的所述寄存器数据存储器的N个寄存器中的数据元素; 执行重排操作以在常规N路交错顺序和解交织顺序之间重新排列源数据元素，以便产生结果数据元素的序列; 并输出用于存储在寄存器数据存储器中的结果数据元素的序列。这提供了一种特别有效的技术，用于执行N路交错和解交织操作，其中N是奇数，导致高性能，低能量消耗和降低的寄存器使用，与已知的现有技术相比。

5. 发明授权

US07761693B2 Data processing apparatus and method for performing arithmetic operations in SIMD data processing 有权
标题翻译：用于在SIMD数据处理中执行算术运算的数据处理装置和方法
公开(公告)号：US07761693B2
公开(公告)日：2010-07-20
申请号：US10889362
申请日：2004-07-13
申请人： Dominic Hugo Symes , Simon Andrew Ford
发明人： Dominic Hugo Symes , Simon Andrew Ford
IPC分类号： G06F7/38
CPC分类号： G06F9/345 , G06F7/4812 , G06F9/30014 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/30116 , G06F9/30138 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F2207/3828
摘要： A data processing apparatus includes a register data store that stores data elements, an instruction decoder that decodes an “arithmetic returning high half” instruction, and a data processor that performs data processing operations controlled by the instruction decoder. In response to the decoded arithmetic returning high half instruction, the data processor specifies within the register data store one or more source registers to store a plurality of source data elements of a first size, and one or more destination registers to store a corresponding plurality of resultant data elements of a second size. The second size is half the size of the first size. The processor also performs the following operations in parallel on the plurality of source data elements to produce the corresponding plurality of resultant data elements: perform an arithmetic operation on the source registers specified by the instruction to produce a plurality of corresponding intermediate result data elements, form the resultant data elements from information derived from a high half of a corresponding one of the plurality of intermediate result data elements, store the resultant data elements in the destination register.
摘要翻译：数据处理装置包括存储数据元素的寄存器数据存储器，对“算术返回高一半”指令进行解码的指令译码器，以及进行由指令译码器控制的数据处理动作的数据处理器。响应于解码的算术返回高半指令，数据处理器在寄存器数据存储器内指定一个或多个源寄存器来存储多个第一大小的源数据元，以及一个或多个目标寄存器，以存储对应的多个第二大小的结果数据元素。第二大小是第一大小的一半。处理器还在多个源数据元件上并行地执行以下操作以产生相应的多个结果数据元素：对由指令指定的源寄存器执行算术运算以产生多个对应的中间结果数据元素，形式从多个中间结果数据元素的对应的一个的高半部得到的信息的结果数据元素将结果数据元素存储在目的地寄存器中。

6. 发明授权

US07145480B2 Data processing apparatus and method for performing in parallel a data processing operation on data elements 有权
标题翻译：用于对数据元素并行执行数据处理操作的数据处理装置和方法
公开(公告)号：US07145480B2
公开(公告)日：2006-12-05
申请号：US10889472
申请日：2004-07-13
申请人： Simon Andrew Ford , Dominic Hugo Symes
发明人： Simon Andrew Ford , Dominic Hugo Symes
IPC分类号： H03M1/22 , G06F7/38
CPC分类号： G06F9/30167 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30112 , G06F9/30145
摘要： A data processing apparatus and method are provided for performing in parallel a data processing operation on data elements. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements, and processing logic operable to perform data processing operations on data elements. A decoder is operable to decode a data processing instruction, the data processing instruction identifying a lane size and a data element size, the lane size being a multiple of the data element size. Further, the decoder is operable to control the processing logic to define based on the lane size a number of lanes of parallel processing in at least one of the registers, and the processing logic is operable to perform in parallel a data processing operation on the data elements within each lane of parallel processing. This provides significantly improved flexibility in the performance of SIMD operations.
摘要翻译：提供了一种数据处理装置和方法，用于并行地执行关于数据元素的数据处理操作。数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器，以及可操作以对数据元素执行数据处理操作的处理逻辑。解码器可操作以对数据处理指令进行解码，数据处理指令识别通道大小和数据元素大小，通道大小是数据元素大小的倍数。此外，解码器可操作以控制处理逻辑以基于通道大小来限定在至少一个寄存器中的多个并行处理通道，并且处理逻辑可操作以并行执行数据的数据处理操作每个并行处理通道内的元素。这提供了显着提高SIMD操作性能的灵活性。

7. 发明授权

US06958718B2 Table lookup operation within a data processing system 有权
公开(公告)号：US06958718B2
公开(公告)日：2005-10-25
申请号：US10889217
申请日：2004-07-13
申请人： Dominic Hugo Symes , Simon Ford , Andrew Christopher Rose
发明人： Dominic Hugo Symes , Simon Ford , Andrew Christopher Rose
IPC分类号： G06F9/38 , G06F7/00 , G06F9/00 , G06F9/30 , G06F9/305 , G06F9/312 , G06F9/318 , G06F9/35 , G06F9/355 , H03M7/00
CPC分类号： G06F9/3004 , G06F9/30181 , G06F9/342 , G06F9/383
摘要： A table lookup extension instruction is provided in which index values stored within an index register D2 are used to select data elements stored within one or more table registers D0, D1 for storage into corresponding positions within a result register D3. Out-of-range index values result in the corresponding locations within the result register being left unchanged U. In this way, an offset can be applied to index values held and then those index values reused with the table registers D0, D1 being reloaded with a different portion of a table so as to give the effect of a larger table than can be directly supported by the number of table registers available.

8. 发明申请

US20100106944A1 Data processing apparatus and method for performing rearrangement operations 有权
标题翻译：用于执行重排操作的数据处理装置和方法
公开(公告)号：US20100106944A1
公开(公告)日：2010-04-29
申请号：US12588412
申请日：2009-10-14
申请人： Dominic Hugo Symes , Simon Andrew Ford
发明人： Dominic Hugo Symes , Simon Andrew Ford
IPC分类号： G06F9/30
CPC分类号： G06F9/30021 , G06F7/4812 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/30138 , G06F9/3016 , G06F9/30167 , G06F9/30189 , G06F9/345 , G06F9/382 , G06F9/3832 , G06F9/3873 , G06F9/3887 , G06F2207/3828
摘要： A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements. An instruction decoder is responsive to at least one but no more than N rearrangement instructions, where N is an odd plural number, to generate control signals to control the processing circuitry to perform a rearrangement process at least equivalent to: obtaining as source data elements the data elements stored in N registers of said register data store as identified by the at least one re-arrangement instruction; performing a rearrangement operation to rearrange the source data elements between a regular N-way interleaved order and a de-interleaved order in order to produce a sequence of result data elements; and outputting the sequence of result data elements for storing in the register data store. This provides a particularly efficient technique for performing N-way interleave and de-interleave operations, where N is an odd number, resulting in high performance, low energy consumption, and reduced register use when compared with known prior art techniques.
摘要翻译：提供了一种执行重排操作的数据处理装置和方法。数据处理装置具有具有多个寄存器的寄存器数据存储器，每个寄存器存储多个数据元素。处理电路响应于控制信号来对数据元素执行处理操作。指令解码器响应于至少一个但不超过N个重排指令，其中N是奇数复数，以产生控制信号，以控制处理电路执行至少等同于：作为源数据元素的重新排列过程存储在由所述至少一个重新布置指令识别的所述寄存器数据存储器的N个寄存器中的数据元素; 执行重排操作以在常规N路交错顺序和解交织顺序之间重新排列源数据元素，以便产生结果数据元素的序列; 并输出用于存储在寄存器数据存储器中的结果数据元素的序列。这提供了一种特别有效的技术，用于执行N路交错和解交织操作，其中N是奇数，导致高性能，低能量消耗和降低的寄存器使用，与已知的现有技术相比。

9. 发明授权

US07747667B2 Data processing apparatus and method for determining an initial estimate of a result value of a reciprocal operation 有权
标题翻译：用于确定倒数操作的结果值的初始估计的数据处理装置和方法
公开(公告)号：US07747667B2
公开(公告)日：2010-06-29
申请号：US11058421
申请日：2005-02-16
申请人： David Raymond Lutz , Christopher Neal Hinds , Dominic Hugo Symes , Simon Andrew Ford
发明人： David Raymond Lutz , Christopher Neal Hinds , Dominic Hugo Symes , Simon Andrew Ford
IPC分类号： G06F7/38
CPC分类号： G06F7/535 , G06F9/30014 , G06F9/3004 , G06F2207/3824 , G06F2207/5354 , G06F2207/5355 , G06F2207/5356
摘要： A data processing apparatus and method generate an initial estimate of a result value that would be produced by performing a reciprocal operation on an input value. The input value and the result value are either fixed point values or floating point values. The data processing apparatus comprises processing logic for executing instructions to perform data processing operations on data, and a lookup table referenced by the processing logic during generation of the initial estimate of the result value. The processing logic is responsive to an estimate instruction to reference the lookup table to generate, dependent on a modified input value that is within a predetermined range of values, a table output value. For a particular modified input value, the same table output value is generated irrespective of whether the input value is a fixed point value or a floating point value. The initial estimate of the result value is then derivable from the table output value. This provides a particularly efficient technique for performing the initial estimate generation within a data processing apparatus where the reciprocal operation may be performed on either fixed point values or floating point values.
摘要翻译：数据处理装置和方法生成对通过对输入值执行倒数操作而产生的结果值的初始估计。输入值和结果值是固定点值或浮点值。该数据处理装置包括执行用于对数据执行数据处理操作的指令的处理逻辑，以及在生成结果值的初始估计期间由处理逻辑引用的查找表。处理逻辑响应于估计指令以引用查找表，以根据在预定范围内的修改的输入值来生成表输出值。对于特定的修改输入值，无论输入值是固定点值还是浮点值，都会生成相同的表格输出值。结果值的初始估计值可从表输出值推导出来。这提供了用于在数据处理装置中执行初始估计生成的特别有效的技术，其中可以对固定点值或浮点值执行倒数操作。

10. 发明授权

US6002881A Coprocessor data access control 失效
标题翻译：协处理器数据访问控制
公开(公告)号：US6002881A
公开(公告)日：1999-12-14
申请号：US932053
申请日：1997-09-17
申请人： Richard York , David James Seal , Dominic Hugo Symes
发明人： Richard York , David James Seal , Dominic Hugo Symes
IPC分类号： G06F15/16 , G06F9/30 , G06F9/312 , G06F9/32 , G06F9/355 , G06F9/38 , G06F13/12 , G06F9/06
CPC分类号： G06F9/3552 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/325 , G06F9/355 , G06F9/384 , G06F9/3877 , G06F9/3879
摘要： A digital signal processing system comprising a central processing unit core 2, a memory 8 and a coprocessor 4 operates using coprocessor memory access instructions (e.g. LDC, STC). The addressing mode information within these coprocessor memory access instructions (P, U, W, Offset) not only controls the addressing mode used by the central processing unit core 2 but is also used by the coprocessor 4 to determine the number of data words in the transfer being specified such that the coprocessor 4 can terminate the transfer at the appropriate time. Knowledge in advance of the number of words in a transfer is also advantageous in some bus systems, such as those that can be used with synchronous DRAM. The Offset field within the instruction may be used to specify changes to be made in the value provided by the central processing unit core 2 upon execution of a particular instruction and also to specify the number of words in the transfer. This arrangement is well suited to working through a regular array of data such as in digital signal processing operations. If the Offset field is not being used, then the number of words to be transferred may default to 1.
摘要翻译：包括中央处理单元核心2，存储器8和协处理器4的数字信号处理系统使用协处理器存储器访问指令（例如LDC，STC）进行操作。这些协处理器存储器访问指令（P，U，W，偏移）内的寻址模式信息不仅控制中央处理单元核心2所使用的寻址模式，而且还由协处理器4使用来确定数据字的数量传输被指定为使得协处理器4可以在适当的时间终止转移。在一些总线系统中，诸如可以与同步DRAM一起使用的那些总线系统中的转移数量之前的知识也是有利的。指令内的偏移字段可以用于指定在执行特定指令时由中央处理单元核心2提供的值进行改变，并且还指定转移中的字数。这种布置非常适合通过数字信号处理操作中的常规数据阵列进行工作。如果未使用偏移字段，则要传输的字数可能默认为1。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式