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1. 发明授权

US07193437B2 Architecture for a connection block in reconfigurable gate arrays 有权
标题翻译：可重构门阵列中连接块的架构
公开(公告)号：US07193437B2
公开(公告)日：2007-03-20
申请号：US10778913
申请日：2004-02-13
申请人： Andrea Cappelli , Luca Ciccarelli , Andrea Lodi , Mario Toma , Fabio Campi
发明人： Andrea Cappelli , Luca Ciccarelli , Andrea Lodi , Mario Toma , Fabio Campi
IPC分类号： H03K19/177 , H01L25/00 , G11C11/00 , G11C7/10
CPC分类号： H03K19/1776 , H01L27/11803 , H03K19/17736
摘要： An optimized architecture to implement connections between logic blocks and routing lines in reconfigurable gate arrays including connection blocks to connect inputs and outputs of different logic elements by means of connection wires, each connection block including a single line of pass transistor switches; and a decoding stage to drive the pass transistor switch.
摘要翻译：一种优化的架构，用于在可重构门阵列中实现逻辑块和路由线之间的连接，包括通过连接线连接不同逻辑元件的输入和输出的连接块，每个连接块包括一行传输晶体管开关; 以及用于驱动传输晶体管开关的解码级。

2. 发明申请

US20060103420A1 Switch block and corresponding switch matrix, in particular for FPGA architectures 有权
标题翻译：开关块和相应的开关矩阵，特别适用于FPGA架构
公开(公告)号：US20060103420A1
公开(公告)日：2006-05-18
申请号：US11215301
申请日：2005-08-30
申请人： Luca Ciccarelli , Carlo Chiesa , Andrea Lodi , Roberto Giansante , Mario Toma , Fabio Campi
发明人： Luca Ciccarelli , Carlo Chiesa , Andrea Lodi , Roberto Giansante , Mario Toma , Fabio Campi
IPC分类号： H03K19/177
CPC分类号： H03K19/17736
摘要： A switch block suitable to realize the connection between interconnection lines connected thereto of the type comprising at least a switching block connected to the interconnection lines and including at least a buffer stage in turn connected to a plurality of transistors. The switch block comprises a decoding stage inserted between a plurality of SRAM cells and respective control terminals of the plurality of transistors of the switching block.
摘要翻译：适于实现连接到其上的互连线之间的连接的开关块，所述互连线至少包括连接到互连线的开关块，并且至少包括缓冲级，并且依次连接到多个晶体管。切换块包括插入在多个SRAM单元与切换块的多个晶体管的各控制端之间的解码级。

3. 发明授权

US07463055B2 Switch block and corresponding switch matrix, in particular for FPGA architectures 有权
标题翻译：开关块和相应的开关矩阵，特别适用于FPGA架构
公开(公告)号：US07463055B2
公开(公告)日：2008-12-09
申请号：US11215301
申请日：2005-08-30
申请人： Luca Ciccarelli , Carlo Chiesa , Andrea Lodi , Roberto Giansante , Mario Toma , Fabio Campi
发明人： Luca Ciccarelli , Carlo Chiesa , Andrea Lodi , Roberto Giansante , Mario Toma , Fabio Campi
IPC分类号： H03K19/173
CPC分类号： H03K19/17736
摘要： A switch block suitable to realize the connection between interconnection lines connected thereto of the type comprising at least a switching block connected to the interconnection lines and including at least a buffer stage in turn connected to a plurality of transistors. The switch block comprises a decoding stage inserted between a plurality of SRAM cells and respective control terminals of the plurality of transistors of the switching block.
摘要翻译：适于实现连接到其上的互连线之间的连接的开关块，所述互连线至少包括连接到互连线的开关块，并且至少包括缓冲级，并且依次连接到多个晶体管。切换块包括插入在多个SRAM单元与切换块的多个晶体管的各控制端之间的解码级。

4. 发明申请

US20100169857A1 METHOD FOR DESIGNING A HIGH PERFORMANCE ASIC (APPLICATION-SPECIFIC INTEGRATED CIRCUIT) ACCELERATOR 有权
标题翻译：设计高性能ASIC（应用特定集成电路）加速器的方法
公开(公告)号：US20100169857A1
公开(公告)日：2010-07-01
申请号：US12648099
申请日：2009-12-28
申请人： Fabio Campi , Claudio Mucci , Stefano Pucillo , Luca Ciccarelli , Valentina Nardone
发明人： Fabio Campi , Claudio Mucci , Stefano Pucillo , Luca Ciccarelli , Valentina Nardone
IPC分类号： G06F17/50 , G06F15/76 , G06F9/06
CPC分类号： G06F17/5068 , G06F2217/64
摘要： A method is for designing an accelerator for digital signal processing including defining a software programmable fully pre-laid out macro by pre-laying out with a fixed topology a control logic of the DSP accelerator to obtain a fully pre-laid out control logic. The method further includes defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area, thereby mapping a computational logic based on computation kernels related to an application of the DSP accelerator. A partially pre-laid out computational logic is therefore obtained.
摘要翻译：一种用于设计用于数字信号处理的加速器的方法，包括通过用固定拓扑预先布置DSP加速器的控制逻辑来定义可完全预编程的软件，以获得完全预先布置的控制逻辑。该方法还包括通过定制可配置布局区域来定义硬件可编程部分预布置的宏，从而基于与DSP加速器的应用相关的计算内核映射计算逻辑。因此获得部分预先布置的计算逻辑。

5. 发明授权

US08910103B2 Method of designing a high performance application specific integrated circuit accelerator 有权
标题翻译：设计高性能专用集成电路加速器的方法
公开(公告)号：US08910103B2
公开(公告)日：2014-12-09
申请号：US12648099
申请日：2009-12-28
申请人： Fabio Campi , Claudio Mucci , Stefano Pucillo , Luca Ciccarelli , Valentina Nardone
发明人： Fabio Campi , Claudio Mucci , Stefano Pucillo , Luca Ciccarelli , Valentina Nardone
IPC分类号： G06F17/50 , G06F15/76 , G06F9/30
CPC分类号： G06F17/5068 , G06F2217/64
摘要： A method is for designing an accelerator for digital signal processing including defining a software programmable fully pre-laid out macro by pre-laying out with a fixed topology a control logic of the DSP accelerator to obtain a fully pre-laid out control logic. The method further includes defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area, thereby mapping a computational logic based on computation kernels related to an application of the DSP accelerator. A partially pre-laid out computational logic is therefore obtained.
摘要翻译：一种用于设计用于数字信号处理的加速器的方法，包括通过用固定拓扑预先布置DSP加速器的控制逻辑来定义可完全预编程的软件，以获得完全预先布置的控制逻辑。该方法还包括通过定制可配置布局区域来定义硬件可编程部分预布置的宏，从而基于与DSP加速器的应用相关的计算内核映射计算逻辑。因此获得部分预先布置的计算逻辑。

6. 发明授权

US07463067B2 Switch block for FPGA architectures 有权
标题翻译： FPGA架构的开关块
公开(公告)号：US07463067B2
公开(公告)日：2008-12-09
申请号：US11537781
申请日：2006-10-02
申请人： Luca Ciccarelli , Andrea Lodi , Roberto Giansante , Luca Magagni , Roberto Canegallo , Roberto Guerrieri
发明人： Luca Ciccarelli , Andrea Lodi , Roberto Giansante , Luca Magagni , Roberto Canegallo , Roberto Guerrieri
IPC分类号： H03K19/094
CPC分类号： H03K19/177
摘要： A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.
摘要翻译：用于结合硬件和软件技术的FPGA架构的开关块，以减少主动和待机泄漏功率。

7. 发明授权

US07683674B2 T-switch buffer, in particular for FPGA architectures 有权
标题翻译： T开关缓冲器，特别适用于FPGA架构
公开(公告)号：US07683674B2
公开(公告)日：2010-03-23
申请号：US11810792
申请日：2007-06-06
申请人： Luca Ciccarelli , Andrea Lodi
发明人： Luca Ciccarelli , Andrea Lodi
IPC分类号： H03K19/094
CPC分类号： H03K17/693 , H03K19/17736 , H03K19/17784
摘要： An embodiment of the invention relates to a T-switch for connecting first, second and third lines and comprising an input section in turn including first, second and third input pass transistors, each connecting a respective line with a first internal node of the T-switch, an output section in turn including first, second and third output pass transistors, each connecting a respective line with a second internal node of the T-switch, and a single buffer stage connected to a first and a second voltage reference and inserted between the first and second internal node.
摘要翻译：本发明的实施例涉及一种用于连接第一，第二和第三线路的T开关，并且包括输入部分，其依次包括第一，第二和第三输入传输晶体管，每个输入传输晶体管将相应的线路与T形开关的第一内部节点连接，开关，输出部分依次包括第一，第二和第三输出传输晶体管，每个输出传输晶体管将相应的线路与T开关的第二内部节点连接，以及单个缓冲级，其连接到第一和第二参考电压并插入在第一和第二内部节点。

8. 发明申请

US20070279088A1 T-switch buffer, in particular for FPGA architectures 有权
标题翻译： T开关缓冲器，特别适用于FPGA架构
公开(公告)号：US20070279088A1
公开(公告)日：2007-12-06
申请号：US11810792
申请日：2007-06-06
申请人： Luca Ciccarelli , Andrea Lodi
发明人： Luca Ciccarelli , Andrea Lodi
IPC分类号： H03K19/173
CPC分类号： H03K17/693 , H03K19/17736 , H03K19/17784
摘要： An embodiment of the invention relates to a T-switch for connecting first, second and third lines and comprising an input section in turn including first, second and third input pass transistors, each connecting a respective line with a first internal node of the T-switch, an output section in turn including first, second and third output pass transistors, each connecting a respective line with a second internal node of the T-switch, and a single buffer stage connected to a first and a second voltage reference and inserted between the first and second internal node.
摘要翻译：本发明的实施例涉及一种用于连接第一，第二和第三线路的T开关，并且包括输入部分，其依次包括第一，第二和第三输入传输晶体管，每个输入传输晶体管将相应的线路与T形开关的第一内部节点连接，开关，输出部分依次包括第一，第二和第三输出传输晶体管，每个输出传输晶体管将相应的线路与T开关的第二内部节点连接，以及单个缓冲级，其连接到第一和第二参考电压并插入在第一和第二内部节点。

9. 发明申请

US20070085563A1 SWITCH BLOCK FOR FPGA ARCHITECTURES 有权
标题翻译： FPGA架构的开关块
公开(公告)号：US20070085563A1
公开(公告)日：2007-04-19
申请号：US11537781
申请日：2006-10-02
申请人： Luca Ciccarelli , Andrea Lodi , Roberto Giansante , Luca Magagni , Roberto Canegallo , Roberto Guerrieri
发明人： Luca Ciccarelli , Andrea Lodi , Roberto Giansante , Luca Magagni , Roberto Canegallo , Roberto Guerrieri
IPC分类号： H03K19/177
CPC分类号： H03K19/177
摘要： A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.
摘要翻译：用于结合硬件和软件技术的FPGA架构的开关块，以减少主动和待机泄漏功率。

10. 发明授权

US07808276B2 Chip-to-chip communication system and method 有权
标题翻译：芯片到芯片通信系统和方法
公开(公告)号：US07808276B2
公开(公告)日：2010-10-05
申请号：US11519444
申请日：2006-09-11
申请人： Luca Ciccarelli , Luca Magagni , Alberto Fazzi , Roberto Canegallo , Roberto Guerrieri
发明人： Luca Ciccarelli , Luca Magagni , Alberto Fazzi , Roberto Canegallo , Roberto Guerrieri
IPC分类号： H03K19/094
CPC分类号： H01L25/0657 , G06F13/4077 , H01L2225/06527 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Embodiments of the invention relate to a chip-to-chip communication system including a transmitter and a receiver connected to receive respective transmitter and receiver clock signals. The transmitter includes precharge and evaluation blocks connected to each other and to a transmitter clock terminal. The receiver includes a precharge block connected to a receiver clock terminal. The precharge blocks precharge an output terminal of the transmitter and an input terminal of the receiver, respectively, to a value corresponding to a first voltage reference during a low phase of the transmitter clock signal.
摘要翻译：本发明的实施例涉及一种包括发射机和接收机的芯片到芯片通信系统，所述发射机和接收机被连接以接收相应的发射机和接收机时钟信号。发射机包括彼此连接的预充电和评估块以及发射机时钟终端。接收机包括连接到接收机时钟端口的预充电块。预充电块在发送器时钟信号的低相位期间，将发送器的输出端子和接收器的输入端子分别预充电到对应于第一电压基准的值。

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