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1. 发明申请

US20110069742A1 Method and Apparatus for Interference Suppression with Efficient Matrix Inversion in a DS-CDMA System 有权
标题翻译：用于DS-CDMA系统中有效矩阵反演的干扰抑制方法和装置
公开(公告)号：US20110069742A1
公开(公告)日：2011-03-24
申请号：US12948749
申请日：2010-11-17
申请人： Anand P. Narayan , Eric S. Olson , Prashant Jain , John K. Thomas
发明人： Anand P. Narayan , Eric S. Olson , Prashant Jain , John K. Thomas
IPC分类号： H04B1/10 , H04L1/02 , H04B1/7115
CPC分类号： H04B1/71072 , H04B1/7097 , H04B1/7107 , H04B1/71075 , H04B1/7115 , H04B1/7117 , H04B15/00 , H04B2001/71077 , H04B2201/709718 , H04J13/00 , H04J13/0048 , H04L43/08 , H04W24/08
摘要： A receiver in a CDMA system comprises a front end processor that generates a combined signal per source. A symbol estimator processes the combined signal to produce symbol estimates. An S-Matrix Generation module refines these symbol estimates based on the sub channel symbol estimates. An interference canceller is configured for cancelling interference from at least one of the plurality of received signals for producing at least one interference-cancelled signal.
摘要翻译： CDMA系统中的接收机包括每个源产生组合信号的前端处理器。符号估计器处理组合信号以产生符号估计。 S矩阵生成模块基于子信道符号估计来优化这些符号估计。一个干扰消除器被配置为消除来自多个接收信号中的至少一个的干扰，用于产生至少一个干扰消除信号。

2. 发明授权

US08121177B2 Method and apparatus for interference suppression with efficient matrix inversion in a DS-CDMA system 有权
标题翻译：用于DS-CDMA系统中有效矩阵求逆的干扰抑制方法和装置
公开(公告)号：US08121177B2
公开(公告)日：2012-02-21
申请号：US12948749
申请日：2010-11-17
申请人： Anand P. Narayan , Eric S. Olson , Prashant Jain , John K. Thomas
发明人： Anand P. Narayan , Eric S. Olson , Prashant Jain , John K. Thomas
IPC分类号： H04B1/00
CPC分类号： H04B1/71072 , H04B1/7097 , H04B1/7107 , H04B1/71075 , H04B1/7115 , H04B1/7117 , H04B15/00 , H04B2001/71077 , H04B2201/709718 , H04J13/00 , H04J13/0048 , H04L43/08 , H04W24/08
摘要： A receiver in a CDMA system comprises a front end processor that generates a combined signal per source. A symbol estimator processes the combined signal to produce symbol estimates. An S-Matrix Generation module refines these symbol estimates based on the sub channel symbol estimates. An interference canceller is configured for cancelling interference from at least one of the plurality of received signals for producing at least one interference-cancelled signal.
摘要翻译： CDMA系统中的接收机包括每个源产生组合信号的前端处理器。符号估计器处理组合信号以产生符号估计。 S矩阵生成模块基于子信道符号估计来优化这些符号估计。一个干扰消除器被配置为消除来自多个接收信号中的至少一个的干扰，用于产生至少一个干扰消除信号。

3. 发明授权

US07430253B2 Method and apparatus for interference suppression with efficient matrix inversion in a DS-CDMA system 有权
标题翻译：用于DS-CDMA系统中有效矩阵求逆的干扰抑制方法和装置
公开(公告)号：US07430253B2
公开(公告)日：2008-09-30
申请号：US10686828
申请日：2003-10-15
申请人： Eric S. Olson , Anand P. Narayan , Prashant Jain , John K. Thomas
发明人： Eric S. Olson , Anand P. Narayan , Prashant Jain , John K. Thomas
IPC分类号： H04L27/00
CPC分类号： H04B1/71052 , H04B1/7107 , H04B1/7117 , H04B1/712
摘要： The present invention is directed to signal cancellation in spread spectrum communication systems. In particular, the present invention provides method and apparatus for selectively canceling interfering signals, even where symbols to be canceled do not align with symbols associated with a desired signal path. Furthermore, the interference cancellation provided by embodiments of the present invention is capable of functioning to remove interference associated with channels utilizing a symbol length that is different than the symbol length of a desired signal path. In accordance with a further embodiment of the present invention, method and apparatus for efficiently calculating projections to enable signal cancellation are provided.
摘要翻译：本发明涉及扩频通信系统中的信号消除。特别地，本发明提供了用于选择性地消除干扰信号的方法和装置，即使要被取消的符号不与符合期望信号路径的符号对齐。此外，由本发明的实施例提供的干扰消除能够利用不同于期望信号路径的符号长度的符号长度去除与信道相关的干扰。根据本发明的另一实施例，提供了用于有效地计算投影以启用信号消除的方法和装置。

4. 发明申请

US20110096767A1 Systems and Methods for Parallel Signal Cancellation 有权
标题翻译：并行信号消除的系统和方法
公开(公告)号：US20110096767A1
公开(公告)日：2011-04-28
申请号：US12966931
申请日：2010-12-13
申请人： Anand P. Narayan , John K. Thomas , Eric S. Olson
发明人： Anand P. Narayan , John K. Thomas , Eric S. Olson
IPC分类号： H04B7/216 , H04B1/10
CPC分类号： H04B1/126 , H04B1/1027 , H04B1/1081 , H04B1/7105 , H04B1/7107 , H04B1/7117 , H04B1/712 , H04B7/0678 , H04B7/0891 , H04B2001/1045 , H04B2201/70719 , H04B2201/70979 , H04J13/0022 , H04J13/20
摘要： A multi-mode receiver includes a channel decomposition module (e.g., a Rake receiver) for separating a received signal into multipath components, an interference selector for selecting interfering paths and subchannels, a synthesizer for synthesizing interference signals from selected sub channel symbol estimates, and an interference canceller for cancelling selected interference in the received signal. At least one of the channel decomposition module, the synthesizer, and the interference canceller are configurable for processing multi-mode signals.
摘要翻译：多模式接收机包括用于将接收信号分离为多路径分量的信道分解模块（例如，Rake接收机），用于选择干扰路径和子信道的干扰选择器，用于合成来自所选子信道符号估计的干扰信号的合成器，以及干扰消除器，用于消除接收到的信号中的选定干扰。信道分解模块，合成器和干扰消除器中的至少一个可配置用于处理多模信号。

5. 发明授权

US09544044B2 Systems and methods for parallel signal cancellation 有权
标题翻译：并行信号消除的系统和方法
公开(公告)号：US09544044B2
公开(公告)日：2017-01-10
申请号：US12966931
申请日：2010-12-13
申请人： Anand P. Narayan , Eric S. Olson , John K. Thomas
发明人： Anand P. Narayan , Eric S. Olson , John K. Thomas
IPC分类号： H03D1/04 , H03D1/06 , H03K5/01 , H03K6/04 , H04B1/10 , H04L1/00 , H04L25/08 , H04B7/08 , H04B1/7105 , H04B1/7107 , H04B1/7117 , H04B7/06 , H04J13/20 , H04B1/712
CPC分类号： H04B1/126 , H04B1/1027 , H04B1/1081 , H04B1/7105 , H04B1/7107 , H04B1/7117 , H04B1/712 , H04B7/0678 , H04B7/0891 , H04B2001/1045 , H04B2201/70719 , H04B2201/70979 , H04J13/0022 , H04J13/20
摘要： The present invention provides systems and methods for parallel interference suppression. In one embodiment of the invention, a processing engine is used to substantially cancel a plurality of interfering signals within a received signal. The processing engine includes a plurality of matrix generators that are used to generate matrices, each matrix comprising elements of a unique interfering signal selected for cancellation. The processing engine also includes one or more processors that use the matrices to generate cancellation operators. A plurality of applicators applies the cancellation operators to parallel but not necessarily unique input signals to substantially cancel the interfering signals from the input signals. These input signals may include received signals, interference cancelled signals and/or PN codes.
摘要翻译：本发明提供了用于并行干扰抑制的系统和方法。在本发明的一个实施例中，处理引擎用于基本上消除接收信号内的多个干扰信号。处理引擎包括用于生成矩阵的多个矩阵生成器，每个矩阵包括被选择用于取消的唯一干扰信号的元素。处理引擎还包括使用矩阵来生成取消操作符的一个或多个处理器。多个施加器将取消操作者应用于并行但不一定是唯一的输入信号，以基本上抵消来自输入信号的干扰信号。这些输入信号可以包括接收信号，干扰消除信号和/或PN码。

6. 发明授权

US07577186B2 Interference matrix construction 有权
标题翻译：干扰矩阵构造
公开(公告)号：US07577186B2
公开(公告)日：2009-08-18
申请号：US10935015
申请日：2004-09-07
申请人： John K. Thomas , Anand P. Narayan , Eric S. Olson
发明人： John K. Thomas , Anand P. Narayan , Eric S. Olson
IPC分类号： H04B1/00
CPC分类号： H04B1/7105 , H04B1/7107 , H04B1/7117
摘要： The present invention provides systems and methods for interference matrix construction. Such an interference matrix may be used to generate a cancellation operator that when applied to a signal may substantially remove selected interfering signals. In one embodiment of the invention, a system comprises an interference selector configured for selecting one or more interferers for interference cancellation. The system also comprises a matrix generator communicatively coupled to the interference selector and configured for receiving selected interferers from the interference selector. The matrix generator is also configured for generating a matrix having one or more vectors, wherein each vector comprises elements of at least one of the selected interferers. Such an interference matrix and the subsequent generation of the cancellation operator may advantageously provide interference cancellation to systems employing CDMA (e.g., such as cdmaOne and cdma2000), WCDMA, Broadband CDMA, UMTS and GPS signals.
摘要翻译：本发明提供了干涉矩阵构造的系统和方法。这样的干涉矩阵可以用于产生消除操作者，当应用于信号时，可以基本上去除所选择的干扰信号。在本发明的一个实施例中，系统包括被配置用于选择一个或多个干扰源用于干扰消除的干扰选择器。该系统还包括通信地耦合到干扰选择器并被配置为从干扰选择器接收所选择的干扰源的矩阵发生器。矩阵生成器还被配置用于生成具有一个或多个向量的矩阵，其中每个向量包括所选择的干扰源中的至少一个的元素。这样的干扰矩阵和随后的取消算子的产生可以有利地对采用CDMA（例如cdmaOne和cdma2000），WCDMA，宽带CDMA，UMTS和GPS信号的系统提供干扰消除。

7. 发明授权

US07359465B2 Serial cancellation receiver design for a coded signal processing engine 有权
标题翻译：编码信号处理引擎的串行消除接收机设计
公开(公告)号：US07359465B2
公开(公告)日：2008-04-15
申请号：US11103138
申请日：2005-04-11
申请人： Eric S. Olson , Anand P. Narayan , John K. Thomas
发明人： Eric S. Olson , Anand P. Narayan , John K. Thomas
IPC分类号： H03D1/04
CPC分类号： H04B1/7105 , H04B1/7075 , H04B1/709 , H04B1/7103 , H04B1/7117 , H04B2001/70706 , H04B2201/70701 , H04B2201/70715
摘要： A novel serial receiver for a wireless communication system is provided. The communication system comprises: a receiver for receiving a signal y having data parameters; a control processor; the control processor for receiving the signal y and the data parameters; at least two fingers, the control processor for determining which of the data parameters are sent to respective fingers, wherein the at least two fingers have at least a search finger and a tracking finger; and wherein the tracking finger comprises a correlator and a Coded Signal Processing Engine (CSPE), the CSPE for interference cancellation in the reception of the signal y. In addition, numerous other embodiments of the serial receiver are provided along with methods for using the serial receiver.
摘要翻译：提供了一种用于无线通信系统的新型串行接收机。通信系统包括：接收器，用于接收具有数据参数的信号y; 一个控制处理器; 用于接收信号y和数据参数的控制处理器; 至少两个手指，所述控制处理器用于确定哪个数据参数被发送到各个手指，其中所述至少两个手指至少具有搜索指和跟踪指; 并且其中所述跟踪指包括相关器和编码信号处理引擎（CSPE），所述CSPE用于在接收信号y时进行干扰消除。此外，提供串行接收机的许多其它实施例以及使用串行接收机的方法。

8. 发明授权

US07477710B2 Systems and methods for analog to digital conversion with a signal cancellation system of a receiver 有权
标题翻译：具有接收机信号消除系统的模数转换系统和方法
公开(公告)号：US07477710B2
公开(公告)日：2009-01-13
申请号：US11005679
申请日：2004-12-07
申请人： Anand P. Narayan , Eric S. Olson , John K. Thomas
发明人： Anand P. Narayan , Eric S. Olson , John K. Thomas
IPC分类号： H04B1/10
CPC分类号： H04B1/7103 , H04B1/7107
摘要： The present invention provides systems and methods for signal cancellation with a receiver. The receiver comprises a discretizer configured for generating digital signals at different resolutions from a received analog signal. Processing fingers of the receiver generate spreading codes from at least one of the digital signals while a Coded Signal Processing Engine (“CSPE”) substantially cancels interference from at least another one of the digital signals. The spreading codes are transferred to the CSPE where they may be used to construct an interference matrix. One or more cancellation operators may be generated and subsequently applied to the digital signal(s) input to the CSPE to substantially cancel the interference therefrom. The CSPE may adjust the number of bits of the substantially interference cancelled signal(s) to meet a requisite bit width or dynamic range of the receiver. The substantially cancelled signal(s) is then transferred to the processing fingers for further processing.
摘要翻译：本发明提供了一种使用接收机进行信号消除的系统和方法。接收机包括被配置为从接收到的模拟信号产生不同分辨率的数字信号的离散器。接收机的处理手指从数字信号中的至少一个产生扩展码，同时编码信号处理引擎（“CSPE”）基本上消除至少另一个数字信号的干扰。扩展码被传送到CSPE，在那里它们可以被用来建立一个干扰矩阵。可以生成一个或多个取消操作符，并且随后将其应用于输入到CSPE的数字信号，从而基本上消除其干扰。 CSPE可以调整基本上干扰消除的信号的比特数以满足接收机的必要比特宽度或动态范围。然后将基本上取消的信号传送到处理指状物用于进一步处理。

9. 发明授权

US08374299B2 Serial cancellation receiver design for a coded signal processing engine 有权
标题翻译：编码信号处理引擎的串行消除接收机设计
公开(公告)号：US08374299B2
公开(公告)日：2013-02-12
申请号：US13076332
申请日：2011-03-30
申请人： Eric S. Olson , Anand P. Narayan , John K. Thomas
发明人： Eric S. Olson , Anand P. Narayan , John K. Thomas
IPC分类号： H03D1/04
CPC分类号： H04B1/7105 , H04B1/7075 , H04B1/709 , H04B1/7103 , H04B1/7117 , H04B2001/70706 , H04B2201/70701 , H04B2201/70715
摘要： An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data.Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.
摘要翻译：干扰消除接收机在对准发射机定时之后组合来自多个路径的数据，并且使用均衡器或Rake接收机来计算符号估计。从符号估计产生干扰估计，并且在将干扰估计重新对准接收机定时之后组合多个干扰估计。对干扰消除数据的每个段计算符号估计的至少两个段。可以采用各种技术来控制这些操作的等待时间和顺序，并且消除器内的子系统可以使用不同的处理时钟速度。

10. 发明申请

US20110182330A1 Serial cancellation receiver design for a coded signal processing engine 有权
标题翻译：编码信号处理引擎的串行消除接收机设计
公开(公告)号：US20110182330A1
公开(公告)日：2011-07-28
申请号：US13076332
申请日：2011-03-30
申请人： Eric S. Olson , Anand P. Narayan , John K. Thomas
发明人： Eric S. Olson , Anand P. Narayan , John K. Thomas
IPC分类号： H04B1/10
CPC分类号： H04B1/7105 , H04B1/7075 , H04B1/709 , H04B1/7103 , H04B1/7117 , H04B2001/70706 , H04B2201/70701 , H04B2201/70715
摘要： An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data.Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.
摘要翻译：干扰消除接收机在对准发射机定时之后组合来自多个路径的数据，并且使用均衡器或Rake接收机来计算符号估计。从符号估计产生干扰估计，并且在将干扰估计重新对准接收机定时之后组合多个干扰估计。对干扰消除数据的每个段计算符号估计的至少两个段。可以采用各种技术来控制这些操作的等待时间和顺序，并且消除器内的子系统可以使用不同的处理时钟速度。

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