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1. 发明授权

US6094717A Computer processor with a replay system having a plurality of checkers 失效
标题翻译：具有重放系统的计算机处理器具有多个检查器
公开(公告)号：US6094717A
公开(公告)日：2000-07-25
申请号：US126658
申请日：1998-07-31
申请人： Amit A. Merchant , David J. Sager , Darrell D. Boggs , Michael D. Upton
发明人： Amit A. Merchant , David J. Sager , Darrell D. Boggs , Michael D. Upton
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3857 , G06F9/3861
摘要： A computer processor includes a multiplexer having a first input, a second input, a third input, and an output. The processor further includes a scheduler coupled to the multiplexer first input, an execution unit coupled to the multiplexer output, and a replay system that has an input coupled to the multiplexer output. The replay system includes a first checker coupled to the replay system input and the second multiplexer input, and a second checker coupled to the first checker and the third multiplexer input.
摘要翻译：计算机处理器包括具有第一输入，第二输入，第三输入和输出的多路复用器。处理器还包括耦合到多路复用器第一输入的调度器，耦合到多路复用器输出的执行单元和具有耦合到多路复用器输出的输入的重播系统。重播系统包括耦合到重放系统输入和第二多路复用器输入的第一检查器，以及耦合到第一检验器和第三多路复用器输入的第二检验器。

2. 发明授权

US07219349B2 Multi-threading techniques for a processor utilizing a replay queue 有权
标题翻译：使用重放队列的处理器的多线程技术
公开(公告)号：US07219349B2
公开(公告)日：2007-05-15
申请号：US10792154
申请日：2004-03-02
申请人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
发明人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
IPC分类号： G06F9/46 , G06F9/40 , G06F15/76
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.
摘要翻译：提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检验器的多个重播队列或重放队列部分，用于临时存储用于重放的一个或多个指令。在一个实施例中，线程特定的重播队列部分可以各自用于存储每个线程的长等待时间指令，直到长等待时间指令准备执行（例如，已经从外部存储器检索到加载指令的数据）。通过将延迟时间长的指令及其依赖项存储在已停播的一个线程的重放队列部分中，执行资源可用于提高未停滞的其他线程的执行速度。

3. 发明授权

US06385715B1 Multi-threading for a processor utilizing a replay queue 有权
标题翻译：使用重放队列的处理器的多线程
公开(公告)号：US06385715B1
公开(公告)日：2002-05-07
申请号：US09848423
申请日：2001-05-04
申请人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
发明人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
IPC分类号： G06F1500
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.
摘要翻译：提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检验器的多个重播队列或重放队列部分，用于临时存储用于重放的一个或多个指令。在一个实施例中，线程特定的重放队列部分可以各自用于存储每个线程的长延时指令，直到长等待时间指令准备执行（例如，已经从外部存储器检索到加载指令的数据）。通过将延迟时间长的指令及其依赖项存储在已停播的一个线程的重放队列部分中，执行资源可用于提高未停滞的其他线程的执行速度。

4. 发明授权

US6163838A Computer processor with a replay system 失效
标题翻译：具有重播系统的计算机处理器
公开(公告)号：US6163838A
公开(公告)日：2000-12-19
申请号：US106857
申请日：1998-06-30
申请人： Amit A. Merchant , David J. Sager , Darrell D. Boggs
发明人： Amit A. Merchant , David J. Sager , Darrell D. Boggs
IPC分类号： G06F9/38 , G06F15/00
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A computer processor includes a multiplexer having a first input, a second input, and an output, and a scheduler coupled to the multiplexer first input. The processor further includes an execution unit coupled to the multiplexer output. The execution unit is adapted to receive a plurality of instructions from the multiplexer. The processor further includes a replay system coupled to the second multiplexer input and the scheduler. The replay system replays an instruction that has not correctly executed by sending a stop scheduler signal to the scheduler and sending the instruction to the multiplexer.
摘要翻译：计算机处理器包括具有第一输入，第二输入和输出的多路复用器以及耦合到多路复用器第一输入的调度器。处理器还包括耦合到多路复用器输出的执行单元。执行单元适于从多路复用器接收多个指令。处理器还包括耦合到第二多路复用器输入和调度器的重播系统。重播系统通过向调度器发送停止调度器信号并将指令发送到多路复用器来重放未正确执行的指令。

5. 发明授权

US07089409B2 Interface to a memory system for a processor having a replay system 有权
公开(公告)号：US07089409B2
公开(公告)日：2006-08-08
申请号：US10690634
申请日：2003-10-23
申请人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
发明人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
IPC分类号： G06F9/48
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3838 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A processor includes a memory execution unit for executing load and store instructions and a replay system for replaying instructions which have not executed properly. The memory execution unit including an invalid store flag that is set for a store instruction if the replay system detects that the store instruction has not executed properly and is cleared if the store instruction has executed properly. If an invalid store flag is set for a store instruction, the replay system replays load instructions which are programmatically younger than the invalid store instruction until the store instruction executes properly.

6. 发明授权

US06665792B1 Interface to a memory system for a processor having a replay system 有权
标题翻译：与具有重放系统的处理器的存储器系统的接口
公开(公告)号：US06665792B1
公开(公告)日：2003-12-16
申请号：US09475029
申请日：1999-12-30
申请人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
发明人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
IPC分类号： G06F900
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3838 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A processor includes a memory execution unit for executing load and store instructions and a replay system for replaying instructions which have not executed properly. The memory execution unit including an invalid store flag that is set for a store instruction if the replay system detects that the store instruction has not executed properly and is cleared if the store instruction has executed properly. If an invalid store flag is set for a store instruction, the replay system replays load instructions which are programmatically younger than the invalid store instruction until the store instruction executes properly.
摘要翻译：处理器包括用于执行加载和存储指令的存储器执行单元和用于重播没有正确执行的指令的重放系统。如果重放系统检测到存储指令没有正确地执行并且如果存储指令已被正确地执行则被清除，该存储器执行单元包括被设置用于存储指令的无效存储标志。如果为存储指令设置了无效的存储标志，则重放系统将重放比无效存储指令更小的编程加载指令，直到存储指令正确执行。

7. 发明授权

US07200737B1 Processor with a replay system that includes a replay queue for improved throughput 失效
标题翻译：具有重播系统的处理器，包括重播队列，以提高吞吐量
公开(公告)号：US07200737B1
公开(公告)日：2007-04-03
申请号：US09474096
申请日：1999-12-29
申请人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
发明人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
IPC分类号： G06F9/00
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a replay queue coupled to the checker for temporarily storing one or more instructions for replay. The replay queue may be used to store a long latency instruction, such as a load in which data must be retrieved from an external memory device. The long latency instruction and possibly one or more dependent instruction are stored in the replay queue until the long latency instruction is ready to be executed (e.g., data for the load instruction has been retrieved from external memory). Once the long latency instruction is ready to be executed, (e.g., the data is available), the long latency instruction may then be unloaded from the replay queue for re-execution.
摘要翻译：提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检查器的重放队列，用于临时存储用于重放的一个或多个指令。重放队列可以用于存储长延迟指令，例如必须从外部存储器件检索数据的负载。长延迟指令和可能的一个或多个相关指令被存储在重放队列中，直到长延迟指令准备好执行（例如，已从外部存储器检索到加载指令的数据）。一旦长延迟指令准备好执行（例如，数据可用），则可以从重放队列卸载长延迟指令以便重新执行。

8. 发明授权

US08850165B2 Method and apparatus for assigning thread priority in a processor or the like 有权
标题翻译：用于在处理器等中分配线程优先级的方法和装置
公开(公告)号：US08850165B2
公开(公告)日：2014-09-30
申请号：US13155055
申请日：2011-06-07
申请人： David W. Burns , James D. Allen , Michael D. Upton , Darrell D. Boggs , David J. Sager
发明人： David W. Burns , James D. Allen , Michael D. Upton , Darrell D. Boggs , David J. Sager
IPC分类号： G06F9/38 , G06F9/48
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译：在多线程处理器中，线程优先级变量被设置在内存中。线程优先级的实际分配基于线程优先级计数器的到期。为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。

9. 发明申请

US20110239221A1 Method and Apparatus for Assigning Thread Priority in a Processor or the Like 有权
标题翻译：用于在处理器等中分配线程优先级的方法和装置
公开(公告)号：US20110239221A1
公开(公告)日：2011-09-29
申请号：US13155055
申请日：2011-06-07
申请人： David W. Burns , James D. Allen , Michael D. Upton , Darrell D. Boggs , David J. Sager
发明人： David W. Burns , James D. Allen , Michael D. Upton , Darrell D. Boggs , David J. Sager
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译：在多线程处理器中，线程优先级变量被设置在内存中。线程优先级的实际分配基于线程优先级计数器的到期。为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。

10. 发明授权

US07987346B2 Method and apparatus for assigning thread priority in a processor or the like 有权
标题翻译：在处理器等中分配线程优先级的方法和装置
公开(公告)号：US07987346B2
公开(公告)日：2011-07-26
申请号：US13011711
申请日：2011-01-21
申请人： David Burns , James D. Allen , Michael D. Upton , Darrell D. Boggs , David J. Sager
发明人： David Burns , James D. Allen , Michael D. Upton , Darrell D. Boggs , David J. Sager
IPC分类号： G06F9/30
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译：在多线程处理器中，线程优先级变量被设置在内存中。线程优先级的实际分配基于线程优先级计数器的到期。为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。

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