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1. 发明申请

US20190303281A1 SURVIVABILITY GUARANTEES FOR MEMORY TRAFFIC 审中-公开
公开(公告)号：US20190303281A1
公开(公告)日：2019-10-03
申请号：US15941468
申请日：2018-03-30
申请人： Amin Firoozshahian , Vedaraman Greetha , Andreas Kleen , Stephen Van Doren , Omid Azizi , Mahesh Madhav , Mahesh Maddury , Chandan Egbert
发明人： Amin Firoozshahian , Vedaraman Greetha , Andreas Kleen , Stephen Van Doren , Omid Azizi , Mahesh Madhav , Mahesh Maddury , Chandan Egbert
IPC分类号： G06F12/02 , G06F12/06
摘要： Various systems and methods for controlling memory traffic flow rate are described herein. A system for computer memory management, the system comprising: rate control circuitry to: receive a rate exceeded signal from monitoring circuitry, the rate exceeded signal indicating that memory traffic flow from a traffic source exceeds a threshold; receive a distress signal from a memory controller that interfaces with a memory device, the distress signal indicating that the memory device is oversubscribed; and implement throttle circuitry to throttle the memory traffic flow from the traffic source when the rate exceeded signal and the distress signal are both asserted.

2. 发明申请

US20190042461A1 PAUSE COMMUNICATION FROM I/O DEVICES SUPPORTING PAGE FAULTS 审中-公开
公开(公告)号：US20190042461A1
公开(公告)日：2019-02-07
申请号：US15958591
申请日：2018-04-20
申请人： Rupin Vakharwala , Amin Firoozshahian , Stephen Van Doren , Rajesh Sankaran , Mahesh Madhav , Omid Azizi , Andreas Kleen , Mahesh Maddury , Ashok Raj
发明人： Rupin Vakharwala , Amin Firoozshahian , Stephen Van Doren , Rajesh Sankaran , Mahesh Madhav , Omid Azizi , Andreas Kleen , Mahesh Maddury , Ashok Raj
IPC分类号： G06F12/1009 , G06F3/06 , G06F12/0862 , G06F9/38
摘要： A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.

3. 发明申请

US20050188159A1 Computer system supporting both dirty-shared and non dirty-shared data processing entities 审中-公开
标题翻译：支持脏共享和非脏共享数据处理实体的计算机系统
公开(公告)号：US20050188159A1
公开(公告)日：2005-08-25
申请号：US11109113
申请日：2005-04-19
申请人： Stephen Van Doren , Gregory Tierney
发明人： Stephen Van Doren , Gregory Tierney
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0831
摘要： A computer system supports a first set of processors configured to operate in a dirty-shared mode and a second set of processors configured to operate in a non dirty-shared mode. The computer system may include a portion of shared memory that stores data in terms of memory blocks. Upon receiving a snoop read requesting shared access to a memory block held in a dirty state, a dirty-shared processor sends a copy of the memory block to the originator of the snoop read and retains a valid a copy of the block in its cache. Non dirty-shared processors additionally write the block back to main memory in response to snoop reads and may also send a copy to the originator. Until the write back is completed at main memory or another processor is granted write access to the block, the dirty-shared and non dirty-shared processors preferably continue to satisfy subsequent snoop reads targeting the memory block.
摘要翻译：计算机系统支持被配置为以脏共享模式操作的第一组处理器和被配置为以非脏共享模式操作的第二组处理器。计算机系统可以包括按照存储块存储数据的共享存储器的一部分。在接收到读取请求对保持在脏状态的存储器块的共享访问的窥探时，脏共享处理器将存储器块的副本发送到窥探读取的发起者，并将该块的有效复制保留在其高速缓存中。非脏处理共享处理器另外将块重写回主存储器以响应窥探读取，并且还可以将副本发送到发起方。直到在主存储器上完成回写或者另一个处理器被授予对该块的写访问权限时，脏共享和非脏共享处理器优选地继续满足针对存储器块的后续窥探读取。

4. 发明申请

US20050160233A1 System and method to facilitate ordering point migration to memory 失效
标题翻译：系统和方法，方便订单点迁移到内存
公开(公告)号：US20050160233A1
公开(公告)日：2005-07-21
申请号：US10760599
申请日：2004-01-20
申请人： Stephen Van Doren , Gregory Tierney , Simon Steely
发明人： Stephen Van Doren , Gregory Tierney , Simon Steely
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0831
摘要： A system may comprise a first node that includes an ordering point for data, the first node being operative to employ a write-back transaction associated with writing the data back to memory. The first node broadcasts a write-back message to at least one other node in the system in response to an acknowledgement provided by the memory indicating that the ordering point for the data has migrated from the first node to the memory.
摘要翻译：系统可以包括包括数据的排序点的第一节点，第一节点可操作地采用与将数据写回到存储器相关联的回写事务。第一节点响应于由存储器提供的确认指示数据的排序点已经从第一节点迁移到存储器的系统中的至少一个其他节点广播回写消息。

5. 发明授权

US06202126B1 Victimization of clean data blocks 失效
标题翻译：干净数据块的受害
公开(公告)号：US06202126B1
公开(公告)日：2001-03-13
申请号：US08957697
申请日：1997-10-24
申请人： Stephen Van Doren , Simon C. Steely, Jr. , Madhumitra Sharma
发明人： Stephen Van Doren , Simon C. Steely, Jr. , Madhumitra Sharma
IPC分类号： G06F1200
CPC分类号： G06F12/0804 , G06F12/0833
摘要： A method for preventing inadvertent invalidation of data elements in a system having a separate probe queue and fill queue for each central processing unit, is provided wherein a central processing unit stores a clean data element, that would otherwise have been discarded, in a victim data buffer when it is evicted from cache. The central processing unit subsequently issues a clean-victim command to the system control logic when the readmiss or read-miss-modify command, targeting the data element that maps to the same location in cache as the clean data element, is issued. The clean-victim command causes the duplicate tag store to indicate that the clean data element is no longer stored in that central processing unit's cache. While the data is stored therein, the central processing unit cannot issue a probe message that targets that data until the victim data buffer has been deallocated. The central processing unit cannot modify the data element and therefore, if a probe invalidate has previously been issued for the clean version of the data element, it will not be able to inadvertently invalidate a modified version of the data element.
摘要翻译：提供了一种用于防止在具有用于每个中央处理单元的单独的探测队列和填充队列的系统中的数据元素的无意的无效的方法，其中中央处理单元将干脆的数据元素（否则将被丢弃）存储在受害者数据中缓冲区从缓存中逐出。当发出针对映射到与清洁数据元素在高速缓存中的相同位置的数据元素的readmiss或read-miss-modify命令时，中央处理单元随后向系统控制逻辑发出清理受害者命令。 clean-victim命令使重复的标签存储指示干净的数据元素不再存储在该中央处理器的缓存中。当数据存储在其中时，中央处理单元不能发出针对该数据的探测消息，直到受害者数据缓冲器被释放。中央处理单元不能修改数据元素，因此如果先前为数据元素的干净版本发出了探针无效，则它将无法无意中使数据元素的修改版本无效。

6. 发明授权

US6061765A Independent victim data buffer and probe buffer release control utilzing control flag 失效
标题翻译：独立的受害者数据缓冲区和探针缓冲区释放控制利用控制标志
公开(公告)号：US6061765A
公开(公告)日：2000-05-09
申请号：US957505
申请日：1997-10-24
申请人： Stephen Van Doren , Simon C. Steely, Jr. , Robert Eugene Stewart , James Bernard Keller
发明人： Stephen Van Doren , Simon C. Steely, Jr. , Robert Eugene Stewart , James Bernard Keller
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0815 , G06F12/0822
摘要： In accordance with the present invention, a method and apparatus is provided for storing victim data evicted from a cache and for satisfying pending requests or probe messages that target victim data, using a set of victim data buffers coupled to a central processing unit of a computer system. Storage locations referred to as a "victim valid bit" and a "probe valid bit" are associated with each victim data buffer in the computer system to indicate a release condition for the coupled victim data buffer. With such an arrangement, the victim data buffer can be deallocated when the victim valid bit and the probe valid bit have both been cleared.
摘要翻译：根据本发明，提供了一种方法和装置，用于存储从高速缓存中移出的受害者数据，并且使用耦合到计算机的中央处理单元的一组受害者数据缓冲器来满足目标受害者数据的待决请求或探测消息系统。称为“受害者有效位”的存储位置和“探测有效位”与计算机系统中的每个受害者数据缓冲器相关联，以指示耦合的受害者数据缓冲器的释放条件。通过这样的配置，当受害者有效位和探测有效位都被清除时，可以释放受害者数据缓冲区。

7. 发明申请

US20060041724A1 Locked cache line sharing 审中-公开
标题翻译：锁定缓存行共享
公开(公告)号：US20060041724A1
公开(公告)日：2006-02-23
申请号：US10920759
申请日：2004-08-17
申请人： Simon Steely , Stephen Van Doren
发明人： Simon Steely , Stephen Van Doren
IPC分类号： G06F12/00
CPC分类号： G06F12/0815
摘要： A technique to share cache lines among a plurality of bus agents. Embodiments of the invention comprise at least one technique to allow a number of agents, such as a processor or software program being executed by a processor, within a computer system or computer network to access a locked (“owned”) cache line, under certain circumstances, without incurring as much of the operational overhead and resulting performance degradation of many prior art techniques.
摘要翻译：一种用于在多个总线代理之间共享高速缓存行的技术。本发明的实施例包括至少一种技术，以允许在计算机系统或计算机网络内的许多代理（诸如处理器或软件程序）由计算机系统或计算机网络中执行以访问锁定（“拥有”）高速缓存行情况，而不会导致许多现有技术技术的操作开销和所导致的性能下降。

8. 发明申请

US20050160232A1 System and method for conflict responses in a cache coherency protocol with ordering point migration 有权
标题翻译：具有排序点迁移的缓存一致性协议中的冲突响应的系统和方法
公开(公告)号：US20050160232A1
公开(公告)日：2005-07-21
申请号：US10760651
申请日：2004-01-20
申请人： Gregory Tierney , Stephen Van Doren , Simon Steely
发明人： Gregory Tierney , Stephen Van Doren , Simon Steely
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0831
摘要： Systems and methods are disclosed for interaction between different cache coherency protocols. One system may comprise a home node that receives a request for data from a first node in a first cache coherency protocol. A second node provides a conflict response to a request for the data from the home node. The conflict response indicates that an ordering point for the data is migrating according to a second cache coherency protocol, which is different from the first cache coherency protocol.
摘要翻译：公开了用于不同高速缓存一致性协议之间的交互的系统和方法。一个系统可以包括家庭节点，其在第一高速缓存一致性协议中从第一节点接收对数据的请求。第二节点向来自家节点的数据的请求提供冲突响应。冲突响应指示数据的排序点根据与第一高速缓存一致性协议不同的第二高速缓存一致性协议进行迁移。

9. 发明授权

US06353876B1 Cache memory exchange optimized memory organization for a computer system 失效
标题翻译：缓存内存交换计算机系统的优化内存组织
公开(公告)号：US06353876B1
公开(公告)日：2002-03-05
申请号：US09643431
申请日：2000-08-22
申请人： Paul M. Goodwin , Stephen Van Doren
发明人： Paul M. Goodwin , Stephen Van Doren
IPC分类号： G06F1208
CPC分类号： G06F12/0813 , G06F12/0804 , G06F12/0882
摘要： Data coherency in a multiprocessor system is improved and data latency minimized through the use of data mapping “fill” requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the same memory module to which the “victim” data in that CPU's cache must be rewritten. With such an arrangement rewrite latency periods for victim data within the crossbar switch is minimized and the 'ships crossing in the night' problem is avoided.
摘要翻译：改进了多处理器系统中的数据一致性，并且通过使用来自多处理器CPU中的任何一个的数据映射“填充”请求来使数据延迟最小化，使得通过来自相同存储器模块的交叉开关获得所请求的信息，“AD” “CPU缓存中的数据必须重写。通过这样的布置，在横梁开关内的受害者数据的重写延迟时间被最小化并且避免了“夜间交船”问题。

10. 发明授权

US6125429A Cache memory exchange optimized memory organization for a computer system 失效
标题翻译：缓存内存交换计算机系统的优化内存组织
公开(公告)号：US6125429A
公开(公告)日：2000-09-26
申请号：US41513
申请日：1998-03-12
申请人： Paul M. Goodwin , Stephen Van Doren
发明人： Paul M. Goodwin , Stephen Van Doren
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , G06F12/0882 , G06F12/0804
摘要： Data coherency in a multiprocessor system is improved and data latency minimized through the use of data mapping "fill" requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the same memory module to which the "victim" data in that CPUs cache must be rewritten. With such an arrangement rewrite latency periods for victim data within the crossbar switch is minimized and the `ships crossing in the night` problem is avoided.
摘要翻译：改进了多处理器系统中的数据一致性，并且通过使用来自多处理器CPU中的任何一个的数据映射“填充”请求来使数据延迟最小化，使得通过来自相同存储器模块的交叉开关获得所请求的信息，“AD” “CPU缓存中的数据必须重写。通过这样的布置，在横梁开关内的受害者数据的重写延迟时间被最小化并且避免了“夜间交船”问题。

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