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1. 发明授权

US5235644A Probabilistic cryptographic processing method 失效
标题翻译：概率密码处理方法
公开(公告)号：US5235644A
公开(公告)日：1993-08-10
申请号：US546614
申请日：1990-06-29
申请人： Amar Gupta , Butler W. Lampson , William R. Hawe , Joseph J. Tardo , Charles W. Kaufman , Mark F. Kempf , Morrie Gasser , B. J. Herbison
发明人： Amar Gupta , Butler W. Lampson , William R. Hawe , Joseph J. Tardo , Charles W. Kaufman , Mark F. Kempf , Morrie Gasser , B. J. Herbison
IPC分类号： H04L29/02
CPC分类号： H04L29/02
摘要： A decryption method, and associated cryptographic processor, for performing in-line decryption of information frames received from a communication network through a first in-line processing stage. As an information packet is streamed into the cryptographic processor, a determination is made to an acceptable level of probability whether the packet contains data that should be decrypted. The decision whether or not decrypt is made by analyzing the incoming packet header, recognizing a limited number of packet formats, and further parsing the packet to locate any encrypted data and to make sure that the packet is not a segment of a larger message. Falsely decrypted packets are looped back through the cryptographic processor, to regenerate the data that was falsely decrypted. Decryption and encryption are performed in such a manner that a false decryption is completely reversible without loss of data. Special treatment is provided for packets containing data that cannot be divided into an integral number of standard blocks required for decryption processing.
摘要翻译：一种解密方法和相关联的密码处理器，用于通过第一串联处理级来执行从通信网络接收的信息帧的在线解密。当信息分组被流传输到密码处理器中时，确定分组是否包含应被解密的数据的可接受概率水平。通过分析进入的分组报头，识别有限数量的分组格式以及进一步解析分组以定位任何加密的数据并确保分组不是更大的消息的分段来进行解密的决定。虚假解密的数据包通过密码处理器环回，以重新生成被错误解密的数据。执行解密和加密，使得假解密完全可逆而不丢失数据。对于包含不能被分解为解密处理所需的整数个标准块的数据的数据包，提供特殊处理。

2. 发明授权

US5099517A Frame status encoding for communication networks 失效
标题翻译：通信网络的帧状态编码
公开(公告)号：US5099517A
公开(公告)日：1992-03-24
申请号：US546631
申请日：1990-06-29
申请人： Amar Gupta , William R. Hawe , Mark F. Kempf , Ching S. Lee
发明人： Amar Gupta , William R. Hawe , Mark F. Kempf , Ching S. Lee
IPC分类号： H04L29/02
CPC分类号： H04L29/02
摘要： A method and corresponding apparatus for encoding and decoding additional status bits into an existing frame status byte transmitted as part of a packet of information in a communication network. The described scheme provides for the encoding and decoding of two additional status bits, without having to modify the packet format. In the disclosed embodiment of the invention, the additional status bits are used to convey information to a node processor concerning decryption processing of a received information packets.
摘要翻译：一种用于将附加状态位编码和解码为作为通信网络中的信息分组的一部分而传输的现有帧状态字节的方法和相应装置。所描述的方案提供了两个附加状态位的编码和解码，而不必修改分组格式。在本发明所公开的实施例中，附加状态位用于向接收到的信息分组的解密处理的节点处理器传送信息。

3. 发明授权

US5086469A Encryption with selective disclosure of protocol identifiers 失效
标题翻译：加密与选择性披露协议标识符
公开(公告)号：US5086469A
公开(公告)日：1992-02-04
申请号：US546615
申请日：1990-06-29
申请人： Amar Gupta , Charles W. Kaufman , Mark F. Kempf , G. Paul Koning
发明人： Amar Gupta , Charles W. Kaufman , Mark F. Kempf , G. Paul Koning
IPC分类号： H04L29/06
CPC分类号： H04L63/04 , H04L29/06 , H04L63/12 , H04L2212/00
摘要： A method for selective disclosure of the identity of a communication protocol under which an information packet originated, but without incorrectly identifying the protocol in a header accompanying the packet. If there is a need to conceal the identity of the underlying source protocol, a special anonymous protocol identifier is used, instead of the real protocol identifier, in the header of an encrypted information packet. Network monitors can then still provide accurate information concerning traffic on the network, without having this information distorted by the use of incorrect communication protocols. If there is a desire to reveal the underlying protocol, a subnetwork protocol frame format is used to store the protocol identity and signify whether the packet is encrypted. A packet that is of a non-subnetwork protocol can be encapsulated with a subnetwork header containing a special code signifying that there is an encapsulated packet and containing the original protocol identifier.

4. 发明授权

US4878219A Method and apparatus for nodes in network to avoid shrinkage of an interframe gap 失效
标题翻译：网络节点的方法和装置，以避免帧间间隔的收缩
公开(公告)号：US4878219A
公开(公告)日：1989-10-31
申请号：US187208
申请日：1988-04-28
申请人： Charles W. Kaufman , Mark F. Kempf , Jerry D. Hutchison
发明人： Charles W. Kaufman , Mark F. Kempf , Jerry D. Hutchison
IPC分类号： G06F13/38 , G06F12/00 , G11C7/00 , H04J3/06 , H04L7/00 , H04L13/08
CPC分类号： H04L25/05 , H04J3/0632 , G06F2205/102
摘要： An output controller in a repeater node for controlling data transfers in a data communication system in which each node is operated by an independent local clock. Nodes will occasionally delete idle bytes from a preamble to recenter an elasticity buffer. The output controller performs a process that requires the elasticity buffer to be progressively more full before deleting another idle byte from the preamble. Transmission of the start of a subsequent frame is delayed and additional idle bytes are transmitted when the number of idle bytes being transmitted is at or below a certain threshold. Multiple thresholds are utilized so that the amount of the delay can be adjusted.

5. 发明授权

US4597078A Bridge circuit for interconnecting networks 失效
标题翻译：桥接电路互连网络
公开(公告)号：US4597078A
公开(公告)日：1986-06-24
申请号：US543242
申请日：1983-10-19
申请人： Mark F. Kempf
发明人： Mark F. Kempf
IPC分类号： H04L12/46 , H04L12/56 , H04J3/26
CPC分类号： H04L12/4625 , H04L45/742 , H04L49/351
摘要： The present system includes logic circuitry to be connected between at least two networks. When a message is sent by a station in a first network, the destination part of the message will be examined by the logic circuitry to see if the destination address has been recorded (stored) and if so to what network the destination station belongs. If the destination address is located in the sending network, the message is not sent to the non-sending network. If the destination address is located in the non-sending network, the message will be sent thereto. If the destination address is not recorded, i.e., it represents a new station, the message will be sent to the non-sending network (such a message is automatically sent to its own network). In the latter case when such a new station becomes a source station, its address will be recorded so that the next time such a station is a destination, the system will know in which network it is located. Further the present system removes from its stored addresses those addresses which are seldom used.
摘要翻译：本系统包括要连接在至少两个网络之间的逻辑电路。当消息由第一网络中的站发送时，消息的目的地部分将被逻辑电路检查，以查看目的地地址是否已被记录（存储），如果目的地址已被存储到目的站所属的网络。如果目的地址位于发送网络中，则该消息不会发送到非发送网络。如果目的地址位于非发送网络中，那么该消息将被发送给它。如果目的地地址未被记录，即它表示新的站，则该消息将被发送到非发送网络（这样的消息被自动发送到其自己的网络）。在后一种情况下，当这样的新站变成源站时，其地址将被记录，使得下一次这样的站是目的地时，系统将知道它在哪个网络中。此外，本系统从其存储的地址中删除那些很少使用的那些地址。

6. 发明授权

US4355354A Interface apparatus for coupling a minicomputer to a microcomputer for the transfer of data between them and method for using same 失效
标题翻译：用于将小型计算机耦合到微型计算机以用于它们之间的数据传送的接口装置和使用它们的方法
公开(公告)号：US4355354A
公开(公告)日：1982-10-19
申请号：US920408
申请日：1978-06-29
申请人： Mark F. Kempf , D'Arcy C. Randall , Timothy R. Walworth
发明人： Mark F. Kempf , D'Arcy C. Randall , Timothy R. Walworth
IPC分类号： G06F3/14 , G06F3/153 , G06F13/28 , G06F15/17 , G06F3/00
CPC分类号： G06F15/17 , G06F13/28 , G06F3/14 , G06F3/153
摘要： Interface apparatus which facilitates asynchronous parallel transfer of data at a speed of up to at least 1.6 megabits per second between a minicomputer and a microcomputer. The apparatus includes a plurality of bidirectional data circuits parallel coupled between the minicomputer and the microcomputer for carrying data between the minicomputer and the microcomputer when either computer wants to send data to the other computer. The apparatus also includes data transfer control circuitry coupled between the minicomputer and the microcomputer for permitting either computer, when it wants to send data, to: (a) indicate by means of a first or second control signal to the receiving computer that the sending computer wants to transmit data over the data circuits, (b) resolve contention between the computers for access to the interface apparatus, (c) enable the receiving computer to indicate to the sending computer that the receiving computer is ready to receive data over the data circuits, (d) effect transfer of data from the sending computer to the receiving computer over the data circuits, and, (e) enable the receiving computer to indicate to the sending computer that the receiving computer has received the data.
摘要翻译：接口装置，其便于在小型计算机和微型计算机之间以高达至少1.6兆比特每秒的速度异步并行传输数据。该装置包括并行耦合在小型计算机和微型计算机之间的多个双向数据电路，用于在计算机希望向其他计算机发送数据时，在小型计算机和微型计算机之间传送数据。该装置还包括耦合在小型计算机和微型计算机之间的数据传输控制电路，用于允许任一计算机在要发送数据时：（a）借助于第一或第二控制信号向接收计算机指示发送计算机希望通过数据电路传输数据，（b）解决用于访问接口设备的计算机之间的争用，（c）使得接收计算机能够向发送计算机指示接收计算机准备好通过数据电路接收数据，（d）通过数据电路将数据从发送计算机传送到接收计算机，以及（e）使得接收计算机向发送计算机指示接收计算机已经接收到数据。

7. 发明授权

US4320452A Digital bus and control circuitry for data routing and transmission 失效
标题翻译：用于数据路由和传输的数字总线和控制电路
公开(公告)号：US4320452A
公开(公告)日：1982-03-16
申请号：US920409
申请日：1978-06-29
申请人： Mark F. Kempf , D'Arcy C. Randall , Timothy R. Walworth
发明人： Mark F. Kempf , D'Arcy C. Randall , Timothy R. Walworth
IPC分类号： G06F13/374 , G06F13/40 , G06F13/42 , G06F15/16
CPC分类号： G06F13/4213 , G06F13/374 , G06F13/4072
摘要： The digital bus is an asynchronous, linear, open-ended digital bus which is coupled to two or more computer/controllers. The bus includes address control circuit lines comprising a bus busy line used by a controller to assert a bus busy signal thereon to gain control of the bus, and to determine if another computer/controller is using the bus, a receiver computer/controller request line used by a controller for requesting permission to send data to another controller, and a receiver computer/controller ready line used by a controller for indicating that that controller is ready to receive data. Data control circuit lines are also provided comprising a data ready line used by a controller for placing a ready-to-send-data signal thereon and a data accept line used by a controller for placing a ready-to-accept-data signal thereon. Also, address bus circuit lines are provided comprising five binary address lines used by a controller for placing an address thereon, which address can have up to five bits. The bus further includes sixteen data bus circuit lines coupled to the two or more controllers. Data to be transferred by a controller is placed on the data circuit lines. A voltage source is coupled to the digital bus lines for pulling up the voltage on all the digital bus lines to the voltage level of the voltage source to make certain that clear signals are provided on the bus and noise problems are avoided. The controllers use the digital bus to asynchronously transfer data and to resolve contention problems between different controllers when they try to gain control of the bus at the same time.
摘要翻译：数字总线是一个异步的，线性的，开放式的数字总线，耦合到两个或更多的计算机/控制器。总线包括地址控制电路线，包括由控制器使用的总线忙线，以在其上断言总线忙信号以获得总线的控制，以及确定另一计算机/控制器是否正在使用总线;接收机计算机/控制器请求线由控制器用于请求向另一控制器发送数据的许可，以及由控制器用于指示该控制器准备好接收数据的接收机计算机/控制器就绪线。还提供了数据控制电路线，包括由控制器使用的数据就绪线，用于在其上放置准备发送数据信号，以及由控制器使用的数据接受线，用于在其上放置准备接收数据信号。而且，提供地址总线电路线，包括由控制器使用的五个二进制地址线，用于在其上放置地址，该地址可以具有多达五位。总线还包括耦合到两个或更多个控制器的16个数据总线电路线。要由控制器传送的数据放在数据电路线上。电压源耦合到数字总线，用于将所有数字总线上的电压提升到电压源的电压电平，以确保在总线上提供清晰的信号，并避免噪声问题。控制器使用数字总线异步传输数据并解决不同控制器之间的争用问题，当他们尝试同时获得总线控制时。

8. 发明授权

US5812774A System for transmitting data packet from buffer by reading buffer descriptor from descriptor memory of network adapter without accessing buffer descriptor in shared memory 失效
标题翻译：通过从网络适配器的描述符存储器读取缓冲器描述符而不访问共享存储器中的缓冲区描述符来从缓冲器发送数据包的系统
公开(公告)号：US5812774A
公开(公告)日：1998-09-22
申请号：US779728
申请日：1997-01-06
申请人： Mark F. Kempf , Henry Sho-Che Yang
发明人： Mark F. Kempf , Henry Sho-Che Yang
IPC分类号： G06F13/38 , G06F13/00
CPC分类号： G06F13/387
摘要： The problems of meeting tight latency requirement while keeping network design low in cost and complexity are solved by the present invention of a network controller with a transaction logic block and a descriptor memory. The invention allows the data buffers and the buffer descriptors to be located in two physically separate memory subsystems. Data buffers can reside in a main system memory which are shared by other system clients. The buffer descriptors, which typically require significantly less memory space than data buffers, can reside in a special dedicated memory which can be low cost. The invention provides a method to allow buffer descriptors to be located in a low latency memory, which can be local to the network adapter. The data buffers can be located in a system shared memory. This design allows system shared resources, e.g. main system memory or bus, to be designed with relatively longer delay budget. This provides a significant system benefit since the buffer memory size is typically many orders of magnitude larger than the buffer descriptor memory size. The invention also provides a method where a system bus supports a priority service where low latency is guaranteed. In this embodiment, the data buffers and the descriptors can reside in a shared memory. The network controller uses the priority service when accessing the buffer descriptors.
摘要翻译：通过具有事务逻辑块和描述符存储器的网络控制器的本发明来解决在保持网络设计成本低和复杂性方面满足紧密等待时间要求的问题。本发明允许数据缓冲器和缓冲器描述符位于两个物理分离的存储器子系统中。数据缓冲区可以驻留在由其他系统客户端共享的主系统存储器中。缓冲区描述符通常需要比数据缓冲区少得多的存储空间，可以驻留在特殊的专用存储器中，这可以是低成本的。本发明提供了一种允许缓冲器描述符位于低延迟存储器中的方法，该低延迟存储器可以是网络适配器本地的。数据缓冲区可以位于系统共享存储器中。该设计允许系统共享资源，例如主系统存储器或总线，设计具有相对较长的延迟预算。这提供了显着的系统优点，因为缓冲存储器大小通常比缓冲器描述符存储器大小许多数量级。本发明还提供了一种方法，其中系统总线支持其中保证低等待时间的优先服务。在该实施例中，数据缓冲器和描述符可以驻留在共享存储器中。网络控制器在访问缓冲区描述符时使用优先级服务。

9. 发明授权

US5805808A Real time parser for data packets in a communications network 失效
标题翻译：通信网络中数据包的实时解析器
公开(公告)号：US5805808A
公开(公告)日：1998-09-08
申请号：US838678
申请日：1997-04-09
申请人： Santosh K. Hasani , Satish L. Rege , Mark F. Kempf
发明人： Santosh K. Hasani , Satish L. Rege , Mark F. Kempf
IPC分类号： G06F13/38 , H04L29/06 , G06F13/00
CPC分类号： H04L29/06 , G06F13/385 , H04L45/7453 , H04L69/22
摘要： A parser for reading bits of a packet has a set of logic circuits implemented in a computer chip; a memory interacting with the computer chip, the memory providing first data to the set of logic circuits; means for reading bits from any field of packet into the set of logic circuits, the bits providing second data to the set of logic circuits; means, responsive to the first data and the second data, for the logic circuits to interpret bits of the packet.
摘要翻译：用于读取分组的位的解析器具有在计算机芯片中实现的一组逻辑电路; 与所述计算机芯片相互作用的存储器，所述存储器向所述逻辑电路组提供第一数据; 用于从任何分组领域读取位到所述逻辑电路组中的装置，所述位向所述逻辑电路组提供第二数据; 意味着响应于第一数据和第二数据，逻辑电路解释分组的位。

10. 发明授权

US5293487A Network adapter with high throughput data transfer circuit to optimize network data transfers, with host receive ring resource monitoring and reporting 失效
标题翻译：具有高吞吐量数据传输电路的网络适配器，可优化网络数据传输，主机接收环网资源监控和报告
公开(公告)号：US5293487A
公开(公告)日：1994-03-08
申请号：US815008
申请日：1991-12-27
申请人： Andrew P. Russo , Satish L. Rege , Edward T. Sullivan , Mark F. Kempf
发明人： Andrew P. Russo , Satish L. Rege , Edward T. Sullivan , Mark F. Kempf
IPC分类号： G06F13/12 , H04L29/06 , G06F13/00
CPC分类号： H04L29/06 , G06F13/128
摘要： A network adapter with high throughput data transfer circuit to optimize network data transfers, with host receive ring resource monitoring and reporting is disclosed. Time critical network data is transferred between the network adapter and the host computer system by means of a high throughput data transfer circuit. The high throughput data transfer circuit is designed to provide throughput equal to the bandwidth of a high speed local area network such as the Fiber Distributed Data Interconnect. The high throughput data transfer circuit will inform the local intelligence of the network adapter if the network adapter has used up all host computer system memory allocated for storing data received from the network. Adapter management data is transferred between the network adapter and the host computer system local area network through a lower throughput data transfer circuit.
摘要翻译：具有高吞吐量数据传输电路的网络适配器，用于优化网络数据传输，具有主机接收环网资源监控和报告功能。时间关键网络数据通过高吞吐量数据传输电路在网络适配器和主机系统之间传输。高吞吐量数据传输电路被设计为提供等于诸如光纤分布式数据互连的高速局域网的带宽的吞吐量。如果网络适配器耗尽了分配用于存储从网络接收的数据的所有主机系统存储器，则高吞吐量数据传输电路将通知网络适配器的本地智能。适配器管理数据通过较低吞吐量数据传输电路在网络适配器和主机系统局域网之间传输。

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