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    • 1. 发明授权
    • Permuted accelerated LDPC (Low Density Parity Check) decoder
    • 加密LDPC(低密度奇偶校验)解码器
    • US08341489B2
    • 2012-12-25
    • US12512820
    • 2009-07-30
    • Alvin Lai LinAndrew J. Blanksby
    • Alvin Lai LinAndrew J. Blanksby
    • H03M13/00
    • H03M13/13H03M13/1137H03M13/1145H03M13/116H04L1/005H04L1/0057
    • Permuted accelerated LDPC (Low Density Parity Check) decoder. This decoding approach operates by processing, in parallel, selected rows for multiple individual LDPC matrix rows from various sub-matrix rows (e.g., first group of rows from a first sub-matrix row, second group of rows from a second sub-matrix row, etc.). A memory structure of daisy chains is employed for memory management of APP (a posteriori probability) values and also for check edge messages/intrinsic information (λ) values. A first group of daisy chains may be employed for memory management of the APP values, and a second group of daisy chains may be employed for memory management of the check edge messages. These daisy chains operate to effectuate the proper alignment of APP (or gamma(γ)) values and check edge message/intrinsic information (λ) values for their respective updating in successive decoding iterations.
    • 加密LDPC(低密度奇偶校验)解码器。 该解码方法通过并行处理来自各种子矩阵行的多个单独LDPC矩阵行的选择行(例如,来自第一子矩阵行的第一组行,来自第二子矩阵行的第二组行 等)。 菊花链的存储器结构被用于APP(后验概率)值的存储器管理,也用于校验边消息/固有信息(λ)值。 第一组菊花链可用于APP值的存储器管理,并且可以采用第二组菊花链来进行校验边消息的存储器管理。 这些菊花链用于在连续的解码迭代中实现APP(或γ(γ))值的正确对齐并检查边缘消息/固有信息(λ)值以用于它们各自的更新。
    • 2. 发明授权
    • Distributed processing LDPC (low density parity check) decoder
    • 分布式处理LDPC(低密度奇偶校验)解码器
    • US08171375B2
    • 2012-05-01
    • US13096114
    • 2011-04-28
    • Alvin Lai LinAndrew J. Blanksby
    • Alvin Lai LinAndrew J. Blanksby
    • H03M13/00
    • H03M13/6516H03M13/1111H03M13/1137H03M13/6505
    • Distributed processing LDPC (Low Density Parity Check) decoder. A means is presented herein that includes an LDPC decoding architecture leveraging a distributed processing technique (e.g., daisy chain) to increase data throughput and reduce memory storage requirements. Routing congestion and critical path latency are also improved thereby. Each daisy chain includes a number of registers, and a number of localized MUXs (e.g., MUXs having merely 2 inputs each). The means presented herein also does not contain any barrel shifters, high fan-in multiplexers, or interconnection networks; therefore, the critical path is relatively short and it can also be pipelined to further increase data throughput. If desired, a communication device can include multiple configurations of such daisy chains to accommodate the decoding of various LDPC coded signals (e.g., such as for an application and/or communication device that must decoded LDPC codes using different low density parity check matrices).
    • 分布式处理LDPC(低密度奇偶校验)解码器。 本文提供了一种包括利用分布式处理技术(例如,菊花链)来增加数据吞吐量并减少存储器存储需求的LDPC解码架构的手段。 路由拥塞和关键路径延迟也因此得到改善。 每个菊花链包括多个寄存器和多个本地化MUX(例如,每个仅具有2个输入的MUX)。 本文中提供的方法也不包含任何桶形移位器,高风扇多路复用器或互连网络; 因此,关键路径相对较短,并且还可以流水线化以进一步增加数据吞吐量。 如果需要,通信设备可以包括这种菊花链的多种配置,以适应各种LDPC编码信号(例如,对于应用和/或通信设备的解码,该应用和/或通信设备必须使用不同的低密度奇偶校验矩阵解码LDPC码)。
    • 3. 发明申请
    • ACCUMULATING LDPC (LOW DENSITY PARITY CHECK) DECODER
    • 累积LDPC(低密度奇偶校验)解码器
    • US20130139026A1
    • 2013-05-30
    • US13726159
    • 2012-12-23
    • Andrew J. BlanksbyAlvin Lai Lin
    • Andrew J. BlanksbyAlvin Lai Lin
    • H03M13/13
    • H03M13/13H03M13/1137H03M13/1145H03M13/116H04L1/005H04L1/0057
    • The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.
    • 本文描述的累积解码架构可应用于由奇偶校验矩阵H操作的LDPC码,H由CSI(循环移位身份)子矩阵(或矩阵子块)或置换的身份子矩阵(或矩阵子块 )。 在这种结构中,整个LDPC矩阵被分解为方形子矩阵,使得每个子矩阵由CSI子矩阵或置换的身份子矩阵或空矩阵组成。 迭代解码过程通过更新APP(后验概率)或伽马(gamma)值和检查边缘消息(lambda)值来操作,并且这通过更新多个子矩阵行(或全部子帧)中的一个或多个单独的行来操作 - 矩阵或子块行)并行处理。 并行度由设计者指定,通常是子矩阵(或子块)大小的整数除数。
    • 4. 发明授权
    • Accumulating LDPC (low density parity check) decoder
    • 累积LDPC(低密度奇偶校验)解码器
    • US08341488B2
    • 2012-12-25
    • US12512490
    • 2009-07-30
    • Andrew J. BlanksbyAlvin Lai Lin
    • Andrew J. BlanksbyAlvin Lai Lin
    • H03M13/00
    • H03M13/13H03M13/1137H03M13/1145H03M13/116H04L1/005H04L1/0057
    • Accumulating LDPC (Low Density Parity Check) decoder. The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.
    • 累积LDPC(低密度奇偶校验)解码器。 本文描述的累积解码架构可应用于由奇偶校验矩阵H操作的LDPC码,H由CSI(循环移位身份)子矩阵(或矩阵子块)或置换的身份子矩阵(或矩阵子块 )。 在这种结构中,整个LDPC矩阵被分解为方形子矩阵,使得每个子矩阵由CSI子矩阵或置换的身份子矩阵或空矩阵组成。 迭代解码过程通过更新APP(后验概率)或γ(γ)值并检查边缘消息(λ)值来操作,并且通过更新多个子矩阵行(或全部子帧)中的一个或多个单独行 - 矩阵或子块行)并行处理。 并行度由设计者指定,通常是子矩阵(或子块)大小的整数除数。
    • 5. 发明申请
    • Multi-code LDPC (Low Density Parity Check) decoder
    • 多码LDPC(低密度奇偶校验)解码器
    • US20110283161A1
    • 2011-11-17
    • US13191664
    • 2011-07-27
    • Andrew J. BlanksbyAlvin Lai Lin
    • Andrew J. BlanksbyAlvin Lai Lin
    • H03M13/05G06F11/10
    • H03M13/116H03M13/1137H03M13/114H03M13/6516H03M13/6527H03M13/6544H03M13/6566H04L1/0052
    • Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.
    • 多码LDPC(低密度奇偶校验)解码器。 可以使用提供用于解码多个LDPC编码信号中的每一个所需的最小要求的硬件来解码多个LDPC编码信号。 在每个LDPC矩阵(例如,用于解码每个LDPC编码信号)包括公共数量的非零子矩阵的实施例中,在解码每个LDPC编码信号时采用相同数量的存储器。 然而,在对每个LDPC编码信号进行解码时,所采用的那些特定存储器可以是不同的子集。 在每个LDPC码在其各自的LDPC矩阵内包括不同数目的非空子矩阵的实施例中,在解码每个LDPC编码信号时采用不同数量的存储器。 也可以采用解码中的不同程度的并行性,在解码不同的LDPC编码信号时可以采用不同数量的比特引擎和检查引擎。
    • 6. 发明授权
    • Multi-code LDPC (low density parity check) decoder
    • 多码LDPC(低密度奇偶校验)解码器
    • US08010881B2
    • 2011-08-30
    • US11843553
    • 2007-08-22
    • Andrew J. BlanksbyAlvin Lai Lin
    • Andrew J. BlanksbyAlvin Lai Lin
    • H03M13/03
    • H03M13/116H03M13/1137H03M13/114H03M13/6516H03M13/6527H03M13/6544H03M13/6566H04L1/0052
    • Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.
    • 多码LDPC(低密度奇偶校验)解码器。 可以使用提供用于解码多个LDPC编码信号中的每一个所需的最小要求的硬件来解码多个LDPC编码信号。 在每个LDPC矩阵(例如,用于解码每个LDPC编码信号)包括公共数量的非零子矩阵的实施例中,在解码每个LDPC编码信号时采用相同数量的存储器。 然而,在对每个LDPC编码信号进行解码时,所采用的那些特定存储器可以是不同的子集。 在每个LDPC码在其各自的LDPC矩阵内包括不同数目的非空子矩阵的实施例中,在解码每个LDPC编码信号时采用不同数量的存储器。 也可以采用解码中的不同程度的并行性,在解码不同的LDPC编码信号时可以采用不同数量的比特引擎和检查引擎。
    • 7. 发明授权
    • Accumulating LDPC (low density parity check) decoder
    • 累积LDPC(低密度奇偶校验)解码器
    • US08578236B2
    • 2013-11-05
    • US13726159
    • 2012-12-23
    • Andrew J. BlanksbyAlvin Lai Lin
    • Andrew J. BlanksbyAlvin Lai Lin
    • H03M13/00
    • H03M13/13H03M13/1137H03M13/1145H03M13/116H04L1/005H04L1/0057
    • The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.
    • 本文描述的累积解码架构可应用于由奇偶校验矩阵H操作的LDPC码,H由CSI(循环移位身份)子矩阵(或矩阵子块)或置换的身份子矩阵(或矩阵子块 )。 在这种结构中,整个LDPC矩阵被分解为方形子矩阵,使得每个子矩阵由CSI子矩阵或置换的身份子矩阵或空矩阵组成。 迭代解码过程通过更新APP(后验概率)或伽马(gamma)值和检查边缘消息(lambda)值来操作,并且这通过更新多个子矩阵行(或全部子帧)中的一个或多个单独的行来操作 - 矩阵或子块行)并行处理。 并行度由设计者指定,通常是子矩阵(或子块)大小的整数除数。
    • 8. 发明申请
    • Distributed processing LDPC (Low Density Parity Check) decoder
    • 分布式处理LDPC(低密度奇偶校验)解码器
    • US20110202816A1
    • 2011-08-18
    • US13096114
    • 2011-04-28
    • Alvin Lai LinAndrew J. Blanksby
    • Alvin Lai LinAndrew J. Blanksby
    • H03M13/00G06F11/08
    • H03M13/6516H03M13/1111H03M13/1137H03M13/6505
    • Distributed processing LDPC (Low Density Parity Check) decoder. A means is presented herein that includes an LDPC decoding architecture leveraging a distributed processing technique (e.g., daisy chain) to increase data throughput and reduce memory storage requirements. Routing congestion and critical path latency are also improved thereby. Each daisy chain includes a number of registers, and a number of localized MUXs (e.g., MUXs having merely 2 inputs each). The means presented herein also does not contain any barrel shifters, high fan-in multiplexers, or interconnection networks; therefore, the critical path is relatively short and it can also be pipelined to further increase data throughput. If desired, a communication device can include multiple configurations of such daisy chains to accommodate the decoding of various LDPC coded signals (e.g., such as for an application and/or communication device that must decoded LDPC codes using different low density parity check matrices).
    • 分布式处理LDPC(低密度奇偶校验)解码器。 本文提供了一种包括利用分布式处理技术(例如,菊花链)来增加数据吞吐量并减少存储器存储要求的LDPC解码架构的手段。 路由拥塞和关键路径延迟也因此得到改善。 每个菊花链包括多个寄存器和多个本地化MUX(例如,每个仅具有2个输入的MUX)。 本文中提供的方法也不包含任何桶形移位器,高风扇多路复用器或互连网络; 因此,关键路径相对较短,并且还可以流水线化以进一步增加数据吞吐量。 如果需要,通信设备可以包括这种菊花链的多种配置,以适应各种LDPC编码信号(例如,对于应用和/或通信设备的解码,该应用和/或通信设备必须使用不同的低密度奇偶校验矩阵解码LDPC码)。
    • 9. 发明申请
    • Multi-code LDPC (Low Density Parity Check) decoder
    • 多码LDPC(低密度奇偶校验)解码器
    • US20090013238A1
    • 2009-01-08
    • US11843553
    • 2007-08-22
    • Andrew J. BlanksbyAlvin Lai Lin
    • Andrew J. BlanksbyAlvin Lai Lin
    • G06F11/10G06F11/00H03M13/00
    • H03M13/116H03M13/1137H03M13/114H03M13/6516H03M13/6527H03M13/6544H03M13/6566H04L1/0052
    • Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.
    • 多码LDPC(低密度奇偶校验)解码器。 可以使用提供用于解码多个LDPC编码信号中的每一个所需的最小要求的硬件来解码多个LDPC编码信号。 在每个LDPC矩阵(例如,用于解码每个LDPC编码信号)包括公共数量的非零子矩阵的实施例中,在解码每个LDPC编码信号时采用相同数量的存储器。 然而,在对每个LDPC编码信号进行解码时,所采用的那些特定存储器可以是不同的子集。 在每个LDPC码在其各自的LDPC矩阵内包括不同数目的非空子矩阵的实施例中,在解码每个LDPC编码信号时采用不同数量的存储器。 也可以采用解码中的不同程度的并行性,在解码不同的LDPC编码信号时可以采用不同数量的比特引擎和检查引擎。
    • 10. 发明申请
    • DISTRIBUTED PROCESSING LDPC (LOW DENSITY PARITY CHECK) DECODER
    • 分布式处理LDPC(低密度奇偶校验)解码器
    • US20090013237A1
    • 2009-01-08
    • US11828532
    • 2007-07-26
    • Alvin Lai LinAndrew J. Blanksby
    • Alvin Lai LinAndrew J. Blanksby
    • G06F11/10H03M13/00
    • H03M13/6516H03M13/1111H03M13/1137H03M13/6505
    • Distributed processing LDPC (Low Density Parity Check) decoder. A means is presented herein that includes an LDPC decoding architecture leveraging a distributed processing technique (e.g., daisy chain) to increase data throughput and reduce memory storage requirements. Routing congestion and critical path latency are also improved thereby. Each daisy chain includes a number of registers, and a number of localized MUXs (e.g., MUXs having merely 2 inputs each). The means presented herein also does not contain any barrel shifters, high fan-in multiplexers, or interconnection networks; therefore, the critical path is relatively short and it can also be pipelined to further increase data throughput. If desired, a communication device can include multiple configurations of such daisy chains to accommodate the decoding of various LDPC coded signals (e.g., such as for an application and/or communication device that must decoded LDPC codes using different low density parity check matrices).
    • 分布式处理LDPC(低密度奇偶校验)解码器。 本文提供了一种包括利用分布式处理技术(例如,菊花链)来增加数据吞吐量并减少存储器存储要求的LDPC解码架构的手段。 路由拥塞和关键路径延迟也因此得到改善。 每个菊花链包括多个寄存器和多个本地化MUX(例如,每个仅具有2个输入的MUX)。 本文中提供的方法也不包含任何桶形移位器,高风扇多路复用器或互连网络; 因此,关键路径相对较短,并且还可以流水线化以进一步增加数据吞吐量。 如果需要,通信设备可以包括这种菊花链的多种配置,以适应各种LDPC编码信号(例如,对于应用和/或通信设备的解码,该应用和/或通信设备必须使用不同的低密度奇偶校验矩阵解码LDPC码)。