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1. 发明专利

JP2012119701A Process/design methodology to enable high performance logic and analog circuits using single process 有权
标题翻译：使用单一过程实现高性能逻辑和模拟电路的过程/设计方法
公开(公告)号：JP2012119701A
公开(公告)日：2012-06-21
申请号：JP2012003044
申请日：2012-01-11
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： QI XIANG , ALBERT RATNAKUMAR , JEFFREY XIAOCHI TANG , WEICH DIN
IPC分类号： H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/092 , H03F3/343
CPC分类号： G05F3/205 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To provide a method and apparatus for improving analog circuits performance on a mixed-signal process.SOLUTION: A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit including plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source, and the body terminal of the PMOS transistors are coupled to a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.
摘要翻译：要解决的问题：提供一种用于在混合信号处理中提高模拟电路性能的方法和装置。提出了一种使用正向偏置电路设计和改进的混合信号处理来提高模拟电路性能的方法。定义了包括多个NMOS和PMOS晶体管的电路。 NMOS晶体管的主体端子耦合到第一电压源，并且PMOS晶体管的主体端子耦合到第二电压源。通过将第一电压源施加到每个选定的NMOS晶体管的主体端子并将第二电压源施加到每个选择的PMOS晶体管的主体端子来选择性地偏置电路中的晶体管。在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的主体端子提供正向和反向偏置。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2012199545A Low-voltage reference circuit 有权
标题翻译：低电压参考电路
公开(公告)号：JP2012199545A
公开(公告)日：2012-10-18
申请号：JP2012056840
申请日：2012-03-14
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： ALBERT RATNAKUMAR , XIANG QI , MAANGAT SIMARDEEP , JUN LIU
IPC分类号： H01L27/04 , G05F3/30 , H01L21/329 , H01L21/822 , H01L29/88 , H01L29/94
CPC分类号： G05F3/30
摘要： PROBLEM TO BE SOLVED: To provide a reference circuit which operates with a low voltage.SOLUTION: A low-voltage reference circuit can comprise a pair of semiconductor devices. Each of the semiconductor devices can include an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator. The gate insulator is inserted between the metal gate and the n-type semiconductor region, and carriers tunnel through the metal gate and the n-type semiconductor region. The metal gate can have a work function which matches a work function of a p-type polysilicon. The gate insulator can have a thickness smaller than approximately 25 angstroms. The metal gate can form a first terminal in the semiconductor device. The n+ region and the n-type semiconductor region can form a second terminal in the semiconductor device. The second terminal can be coupled to the ground. A bias circuit can use the first terminal so as to supply a different current to the semiconductor device, and can supply a corresponding reference output voltage at a value less than 1 volt.
摘要翻译：要解决的问题：提供以低电压工作的参考电路。解决方案：低压参考电路可以包括一对半导体器件。每个半导体器件可以包括n型半导体区域，n型半导体区域中的n +区域，金属栅极和栅极绝缘体。栅极绝缘体插入在金属栅极和n型半导体区域之间，并且载流子穿过金属栅极和n型半导体区域。金属栅极可以具有匹配p型多晶硅的功函数的功函数。栅极绝缘体可以具有小于约25埃的厚度。金属栅极可以在半导体器件中形成第一端子。 n +区域和n型半导体区域可以在半导体器件中形成第二端子。第二个终端可以耦合到地面。偏置电路可以使用第一端子以向半导体器件提供不同的电流，并且可以以小于1伏的值提供相应的参考输出电压。版权所有（C）2013，JPO＆INPIT

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