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1. 发明授权

US06172937B2 Multiple synthesizer based timing signal generation scheme 有权
标题翻译：基于多合成器的定时信号生成方案
公开(公告)号：US06172937B2
公开(公告)日：2001-01-09
申请号：US09309049
申请日：1999-05-10
申请人： Alper Ilkbahar , Simon M. Tam , Ian A. Young
发明人： Alper Ilkbahar , Simon M. Tam , Ian A. Young
IPC分类号： G11C800
CPC分类号： G06F1/06
摘要： A multiple synthesizer based timing signal generation scheme is described that allows accurate data and strobe generation in high speed source synchronous system interfaces. Multiple loop locked clock synthesizers (e.g., phase locked loops, delay locked loops) are used to generate multiple clock signals. Data and strobe signals are triggered off of transitions of one of the clock signals. Because multiple loop locked clock synthesizers are used to generate the clock signals, optimal or near optimal alignment of the data and strobe signals can be achieved. Improved alignment of the data and strobe signals provides improved data transmission rates.
摘要翻译：描述了基于多合成器的定时信号生成方案，其允许在高速源同步系统接口中进行准确的数据和频闪生成。多环路锁定时钟合成器（例如，锁相环，延迟锁定环）用于产生多个时钟信号。数据和选通信号从一个时钟信号的转换触发。由于使用多个环路锁定时钟合成器来产生时钟信号，所以可以实现数据和选通信号的最佳或接近最佳对准。改进的数据和选通信号的对准提供了改进的数据传输速率。

2. 发明授权

US4961002A Synapse cell employing dual gate transistor structure 失效
标题翻译：突触细胞采用双栅晶体管结构
公开(公告)号：US4961002A
公开(公告)日：1990-10-02
申请号：US419685
申请日：1989-10-11
申请人： Simon M. Tam , Mark A. Holler , Hernan A. Castro
发明人： Simon M. Tam , Mark A. Holler , Hernan A. Castro
IPC分类号： G06N3/063 , G11C15/04
CPC分类号： G06N3/0635 , G06N3/063 , G11C15/046
摘要： A synapse cell for providing a weighted connection between an input voltage line and an output summing line having an associated capacitance. Connection between input and output lines in the associative network is made using a dual-gate transistor. The transistor has a floating gate member for storing electrical charge, a pair of control gates coupled to a pair of input lines, and a drain coupled to an output summing line. The floating gate of the transistor is used for storing a charge which corresponds to the strength or weight of the neural connection. When a binary voltage pulse having a certain duration is applied to either one or both of the control gates of the transistor, a current is generated. This current acts to discharge the capacitance associated with the output summing line. Furthermore, by employing a dual-gate structure, programming disturbance of neighboring devices in the network is practically eliminated.
摘要翻译：一种用于在输入电压线和具有相关电容的输出求和线之间提供加权连接的突触单元。关联网络中的输入和输出线之间的连接是使用双栅极晶体管进行的。晶体管具有用于存储电荷的浮动栅极部件，耦合到一对输入线路的一对控制栅极和耦合到输出求和线路的漏极。晶体管的浮置栅极用于存储对应于神经连接的强度或重量的电荷。当具有一定持续时间的二进制电压脉冲被施加到晶体管的一个或两个控制栅极时，产生电流。该电流用于放电与输出求和线相关联的电容。此外，通过采用双栅结构，实际上消除了网络中相邻设备的编程干扰。

3. 发明授权

US06908227B2 Apparatus for thermal management of multiple core microprocessors 有权
标题翻译：多核心微处理器热管理装置
公开(公告)号：US06908227B2
公开(公告)日：2005-06-21
申请号：US10227125
申请日：2002-08-23
申请人： Stefan Rusu , Simon M. Tam
发明人： Stefan Rusu , Simon M. Tam
IPC分类号： G01K1/02 , G01K7/42 , G06F1/20 , G01K13/00 , G06F1/32
CPC分类号： G06F1/206 , G01K1/026 , G01K7/42 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： An apparatus for managing the temperature of an integrated circuit having a multiple core microprocessor is described. Specifically, thermal sensors are placed at potential hot spots throughout each microprocessor core. A thermal management unit monitors the thermal sensors. If a thermal sensor identifies a hot spot, the thermal management unit adjusts the operating frequency and voltage of that microprocessor core accordingly.
摘要翻译：描述了一种用于管理具有多核微处理器的集成电路的温度的装置。具体来说，热传感器放置在每个微处理器核心的潜在热点。热管理单元监视热传感器。如果热传感器识别热点，则热管理单元相应地调整该微处理器核心的工作频率和电压。

4. 发明授权

US06788156B2 Adaptive variable frequency clock system for high performance low power microprocessors 有权
标题翻译：用于高性能低功耗微处理器的自适应变频时钟系统
公开(公告)号：US06788156B2
公开(公告)日：2004-09-07
申请号：US10456660
申请日：2003-06-06
申请人： Simon M. Tam , Stefan Rusu
发明人： Simon M. Tam , Stefan Rusu
IPC分类号： H03B2800
CPC分类号： G06F1/324 , G06F1/3203 , H03L7/06 , H03L7/0805 , Y02D10/126
摘要： A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.
摘要翻译：一种在处理器中动态地改变时钟频率的方法。一个实施例的方法包括用来自相位锁定环（PLL）的时钟输出来驱动时钟分配网络。可调时钟发生器与锁相环锁定。可调时钟发生器代替时钟分配网络上的PLL。

5. 发明授权

US5268320A Method of increasing the accuracy of an analog circuit employing floating gate memory devices 失效
标题翻译：使用浮动栅极存储器件的模拟电路的精度提高的方法
公开(公告)号：US5268320A
公开(公告)日：1993-12-07
申请号：US865451
申请日：1992-04-09
申请人： Mark A. Holler , Simon M. Tam
发明人： Mark A. Holler , Simon M. Tam
IPC分类号： G06N3/063 , G11C27/00 , H01L29/788 , H01L21/265 , H01L21/76
CPC分类号： G06N3/0635 , G11C27/005 , H01L29/7887 , Y10S438/91
摘要： A method for increasing the accuracy of an analog neural network which computers a sum-of-products between an input vector and a stored weight pattern is described. In one embodiment of the present invention, the method comprises initially training the network by programming the synapses with a certain weight pattern. The training may be carried out using any standard learning algorithm. Preferably, a back-propagation learning algorithm is employed.Next, the network is baked at an elevated temperature to effectuate a change in the weight pattern previously programmed during initial training. This change results from a charge redistribution which occurs within each of the synapses of the network. After baking, the network is then retrained to compensate for the change resulting from the charge redistribution. The baking and retraining steps may be successively repeated to increase the accuracy of the neural network to any desired level.
摘要翻译：描述了一种用于增加计算输入向量和存储的权重模式之和的乘积的模拟神经网络的精度的方法。在本发明的一个实施例中，该方法包括通过以某种权重模式编程突触来初始训练网络。可以使用任何标准学习算法进行训练。优选地，采用反向传播学习算法。接下来，网络在升高的温度下烘烤以实现初始训练中先前编程的重量模式的变化。这种变化是由于网络每个突触中发生的电荷再分配产生的。烘烤后，网络再次进行补充，以补偿由电荷重新分配引起的变化。烘焙和再培训步骤可以连续重复，以将神经网络的精度提高到任何所需的水平。

6. 发明授权

US4957877A Process for simultaneously fabricating EEPROM cell and flash EPROM cell 失效
标题翻译：同时制造EEPROM单元和闪存EPROM单元的工艺
公开(公告)号：US4957877A
公开(公告)日：1990-09-18
申请号：US274420
申请日：1988-11-21
申请人： Simon M. Tam , Stefan K. C. Lai
发明人： Simon M. Tam , Stefan K. C. Lai
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L29/66825 , H01L29/7883
摘要： Improved processing which permits the simultaneous fabrication of block erasable flash EPROM cells and individually erasable EEPROM cells. A polysilicon finger extends from the floating gate of the EEPROM cell over a tunnel oxide region. Doped regions are formed under this finger by implanting dopants in alignment with the finger during the implantation of the source and drain regions for the cells and then driving the dopant under the finger. The arsenic dopant used to form the source and drain regions for the cells is used to form the doped regions along with the phosphorus dopant used for the source region of the flash EPROM cells.
摘要翻译：改进的处理，允许同时制造块可擦除闪存EPROM单元和单独可擦除EEPROM单元。多晶硅指状物从EEPROM单元的浮动栅极延伸穿过隧道氧化物区域。通过在用于单元的源极和漏极区域的注入期间注入与手指对准的掺杂剂，然后在手指下驱动掺杂剂，在该手指下方形成掺杂区域。用于形成用于电池的源极和漏极区域的砷掺杂物用于与用于闪存EPROM单元的源极区域的磷掺杂物一起形成掺杂区域。

7. 发明授权

US4949140A EEPROM cell with integral select transistor 失效
标题翻译：具有积分选择晶体管的EEPROM单元
公开(公告)号：US4949140A
公开(公告)日：1990-08-14
申请号：US338382
申请日：1989-04-12
申请人： Simon M. Tam
发明人： Simon M. Tam
IPC分类号： H01L21/28 , H01L21/336 , H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/7885
摘要： An electrically programmable and electrically erasable floating gate memory device which includes an integrally formed select device. In the n-channel embodiment, a boron region is formed adjacent to the drain region under the control gate and extends slightly under the floating gate. This region is formed using a spacer defined with an anisotropic etching step. The region, in addition to providing enhanced programming, prevents conduction when over-erasing has occurred, that is, when the erasing causes the cell to be depletion-like.
摘要翻译：一种电可编程和电可擦除浮动存储器件，其包括一体形成的选择装置。在n沟道实施例中，在控制栅极下方形成与漏极区域相邻的硼区域，并且在浮动栅极下方稍微延伸。该区域使用由各向异性蚀刻步骤限定的间隔来形成。除了提供增强的编程之外，该区域还防止在发生过度擦除时的传导，即当擦除导致电池耗尽时。

8. 发明授权

US06762629B2 VCC adaptive dynamically variable frequency clock system for high performance low power microprocessors 有权
标题翻译： VCC自适应动态可变频率时钟系统，用于高性能低功耗微处理器
公开(公告)号：US06762629B2
公开(公告)日：2004-07-13
申请号：US10206610
申请日：2002-07-26
申请人： Simon M. Tam , Stefan Rusu
发明人： Simon M. Tam , Stefan Rusu
IPC分类号： H03B1900
CPC分类号： G06F1/324 , G06F1/08 , G06F1/3203 , G06F1/3296 , H03L7/0805 , H03L7/081 , H03L7/18 , H03L7/22 , Y02D10/126 , Y02D10/172
摘要： A method and an apparatus for dynamically varying a clock frequency in a processor to adapt to VCC voltage changes. The method of one embodiment includes sampling a supply voltage at a plurality of locations. The values of said supply voltage are communicated to a clock generator. A clock frequency of a clock signal generated from the clock generator is adjusted in response to an evaluation of the sampled values of the supply voltage.
摘要翻译：一种用于在处理器中动态地改变时钟频率以适应VCC电压变化的方法和装置。一个实施例的方法包括对多个位置处的电源电压进行采样。所述电源电压的值被传送到时钟发生器。响应于对电源电压的采样值的评估，调整从时钟发生器产生的时钟信号的时钟频率。

9. 发明授权

US06201448B1 Method and apparatus to reduce clock jitter of an on-chip clock signal 有权
标题翻译：降低片内时钟信号的时钟抖动的方法和装置
公开(公告)号：US06201448B1
公开(公告)日：2001-03-13
申请号：US09473925
申请日：1999-12-28
申请人： Simon M. Tam , Stefan Rusu
发明人： Simon M. Tam , Stefan Rusu
IPC分类号： H03L706
CPC分类号： H03L7/06 , G06F1/10 , H03L7/081
摘要： An on-die clock generator. For one aspect of the invention, the on-die clock generator includes a phase-locked loop (PLL) circuit having a first input coupled to receive an external clock signal and an output coupled to provide an on-die clock signal to be used during a normal operating mode of an integrated circuit. The on-die clock generator also includes a local clock generator circuit having an input coupled to receive the on-die clock signal and an output coupled to provide a local PLL feedback clock signal to a second input of the PLL.
摘要翻译：一个片上时钟发生器。对于本发明的一个方面，片上时钟发生器包括锁相环（PLL）电路，其具有耦合以接收外部时钟信号的第一输入和耦合以提供待使用的时钟信号的输出集成电路的正常工作模式。片上时钟发生器还包括具有耦合以接收片上时钟信号的输入的本地时钟发生器电路，以及耦合以将本地PLL反馈时钟信号提供给PLL的第二输入的输出。

10. 发明授权

US5087826A Multi-layer neural network employing multiplexed output neurons 失效
标题翻译：多层神经网络采用复用输出神经元
公开(公告)号：US5087826A
公开(公告)日：1992-02-11
申请号：US635231
申请日：1990-12-28
申请人： Mark A. Holler , Simon M. Tam
发明人： Mark A. Holler , Simon M. Tam
IPC分类号： G06F15/18 , G06G7/60 , G06N3/04 , G06N99/00
CPC分类号： G06N3/0445
摘要： A multi-layer electrically trainable analog neural network employing multiplexed output neurons having inputs organized into two groups, external and recurrent (i.e., feedback). Each layer of the network comprises a matrix of synapse cells which implement a matrix multiplication between an input vector and a weight matrix. In normal operation, an external input vector coupled to the first synaptic array generates a Sigmoid response at the output of a set of neurons. This output is then fed back to the next and subsequent layers of the network as a recurrent input vector. The output of second layer processing is generated by the same neurons used in first layer processing. Thus, the neural network of the present invention can handle N-layer operation by using recurrent connections and a single set of multiplexed output neurons.
摘要翻译：一种多层电可训练的模拟神经网络，其使用具有组合成两组的输入的多路复用输出神经元，外部和复发（即，反馈）。网络的每个层包括突变单元的矩阵，其实现输入向量和权重矩阵之间的矩阵乘法。在正常操作中，耦合到第一突触阵列的外部输入向量在一组神经元的输出处产生S形反应。然后将该输出作为反复输入向量反馈到网络的下一层和后续层。第二层处理的输出由第一层处理中使用的相同神经元产生。因此，本发明的神经网络可以通过使用循环连接和单组多路复用输出神经元来处理N层操作。

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