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1. 发明授权

US10732976B2 Integrated circuit processor and method of operating the integrated circuit processor in different modes of differing thread counts 有权
公开(公告)号：US10732976B2
公开(公告)日：2020-08-04
申请号：US14655122
申请日：2013-01-10
申请人： Alistair Robertson , Jeffrey W. Scott
发明人： Alistair Robertson , Jeffrey W. Scott
IPC分类号： G06F9/46 , G06F9/48 , G06F9/38 , G06F9/30 , G06F9/50
摘要： A processor includes an instruction pipeline. The pipeline can be operated alternatively in a multi-thread mode and in a single-thread mode. In the multi-thread mode, the instruction pipeline processes multiple threads in an interleaved or simultaneous manner. In the single-thread mode, the pipeline processes a single thread. The instruction pipeline comprises multiple functional units, each of which is reserved for one thread among the multiple threads when the pipeline is in the multi-thread mode and reserved for one context layer among multiple context layers when the instruction pipeline is in the single-thread mode.

2. 发明授权

US10007522B2 System and method for selectively allocating entries at a branch target buffer 有权
公开(公告)号：US10007522B2
公开(公告)日：2018-06-26
申请号：US14282290
申请日：2014-05-20
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F9/32 , G06F9/42 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/3808 , G06F9/3844
摘要： A branch instruction and a corresponding branch instruction address are received at a data processing system. A first value is received and is compared to a portion of the branch instruction address. An entry at a branch target buffer corresponding to the branch instruction is selectively allocated based on a result of the comparing.

3. 发明授权

US09311099B2 Systems and methods for locking branch target buffer entries 有权
标题翻译：用于锁定分支目标缓冲区条目的系统和方法
公开(公告)号：US09311099B2
公开(公告)日：2016-04-12
申请号：US13955106
申请日：2013-07-31
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F9/22 , G06F9/38
CPC分类号： G06F9/3806
摘要： A data processing system includes a processor configured to execute processor instructions and a branch target buffer having a plurality of entries. Each entry is configured to store a branch target address and a lock indicator, wherein the lock indicator indicates whether the entry is a candidate for replacement, and wherein the processor is configured to access the branch target buffer during execution of the processor instructions. The data processing system further includes control circuitry configured to determine a fullness level of the branch target buffer, wherein in response to the fullness level reaching a fullness threshold, the control circuitry is configured to assert the lock indicator of one or more of the plurality of entries to indicate that the one or more of the plurality of entries is not a candidate for replacement.
摘要翻译：数据处理系统包括被配置为执行处理器指令的处理器和具有多个条目的分支目标缓冲器。每个条目被配置为存储分支目标地址和锁定指示符，其中所述锁定指示符指示所述条目是否是替换的候选，并且其中所述处理器被配置为在所述处理器指令的执行期间访问所述分支目标缓冲器。数据处理系统还包括配置成确定分支目标缓冲器的饱和度水平的控制电路，其中响应于饱和度达到饱和阈值，控制电路被配置为断言多个条目，以指示所述多个条目中的一个或多个条目不是替换候选者。

4. 发明申请

US20150339124A1 SYSTEM AND METHOD FOR SELECTIVELY ALLOCATING ENTRIES AT A BRANCH TARGET BUFFER 有权
标题翻译：在分支目标缓存器中选择分配入口的系统和方法
公开(公告)号：US20150339124A1
公开(公告)日：2015-11-26
申请号：US14282290
申请日：2014-05-20
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3806 , G06F9/3808 , G06F9/3844
摘要： A branch instruction and a corresponding branch instruction address are received at a data processing system. A first value is received and is compared to a portion of the branch instruction address. An entry at a branch target buffer corresponding to the branch instruction is selectively allocated based on a result of the comparing.
摘要翻译：在数据处理系统处接收分支指令和对应的分支指令地址。接收到第一个值，并将其与分支指令地址的一部分进行比较。基于比较的结果，选择性地分配与分支指令对应的分支目标缓冲器中的条目。

5. 发明申请

US20150039945A1 DATA PROCESSOR DEVICE FOR HANDLING A WATCHPOINT AND METHOD THEREOF 有权
标题翻译：用于处理观察点的数据处理器装置及其方法
公开(公告)号：US20150039945A1
公开(公告)日：2015-02-05
申请号：US13955102
申请日：2013-07-31
申请人： WILLIAM C. MOYER , Jeffrey W. Scott
发明人： WILLIAM C. MOYER , Jeffrey W. Scott
IPC分类号： G06F11/34
CPC分类号： G06F11/36 , G06F11/3072 , G06F11/3082 , G06F11/3636
摘要： Upon detecting an occurrence of a watchpoint event for debugging a computer processing system, at least a portion of at least one message in a trace message buffer is flushed when a characteristic of the at least one of the messages matches a specified characteristic.
摘要翻译：当检测到用于调试计算机处理系统的观察点事件的发生时，当所述至少一个消息的特性与指定的特性匹配时，跟踪消息缓冲器中的至少一个消息的至少一部分被刷新。

6. 发明申请

US20140068346A1 DATA PROCESSOR DEVICE FOR HANDLING A WATCHPOINT AND METHOD THEREOF 有权
标题翻译：用于处理观察点的数据处理器装置及其方法
公开(公告)号：US20140068346A1
公开(公告)日：2014-03-06
申请号：US13598240
申请日：2012-08-29
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F11/34
CPC分类号： G06F11/3636
摘要： During a debug mode of operation of a data processor, it is determined at the data processor that a watchpoint event has occurred, and in response, an operating condition of a trace FIFO that stores trace information not yet communicated to a debugger is changed. For example, the occurrence of a FIFO flush watchpoint results in trace information being flushed from the trace FIFO before the trace information has been communicated to a trace analyzer.
摘要翻译：在数据处理器的调试操作模式期间，在数据处理器确定观察点事件已经发生，并且作为响应，存储跟尚未传送到调试器的跟踪信息的跟踪FIFO的操作条件被改变。例如，FIFO追查观察点的发生导致跟踪信息在跟踪信息已被传送到跟踪分析器之前被从跟踪FIFO刷新。

7. 发明授权

US08399910B2 Sub-pixel NBN detector 有权
标题翻译：子像素NBN检测器
公开(公告)号：US08399910B2
公开(公告)日：2013-03-19
申请号：US13153297
申请日：2011-06-03
申请人： Jeffrey W. Scott , Colin E. Jones , Ernie J. Caine , Charles A. Cockrum
发明人： Jeffrey W. Scott , Colin E. Jones , Ernie J. Caine , Charles A. Cockrum
IPC分类号： H01L31/102
CPC分类号： H01L31/035281 , H01L27/146 , H01L27/14601 , H01L27/14603 , H01L27/14638 , H01L27/14643 , H01L27/14694 , H01L31/0304 , H01L31/101 , H01L31/102 , Y02E10/50
摘要： A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.
摘要翻译：制造二维检测器阵列（和这种阵列）的方法包括形成n掺杂的半导体光吸收层的多行和多列单独的检测器中的每一个，形成阻挡层，该阻挡层包括 AlSb，AlAsSb，AlGaAsSb，AlSb，AlGaPSb和HgZnTe中的一种或多种，并且形成n掺杂的半导体接触区域。

8. 发明授权

US08364937B2 Executing misaligned load dependent instruction in second execution stage in parity protected mode in configurable pipelined processor 有权
标题翻译：在可配置流水线处理器中，在奇偶校验保护模式的第二个执行阶段执行未对齐的负载相关指令
公开(公告)号：US08364937B2
公开(公告)日：2013-01-29
申请号：US13446930
申请日：2012-04-13
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/38
CPC分类号： G06F9/3875 , G06F9/3004 , G06F9/30181 , G06F9/30189 , G06F9/38 , G06F9/3861 , G06F9/3867 , G06F11/1004 , G06F11/1008 , G06F11/1076
摘要： A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a load instruction and a data-dependent instruction to the instruction pipeline. Based on an operating mode, such as ECC mode or parity mode, the data-dependent instruction may execute in either the first of the second instruction pipeline stage. Further, the execution of the data-dependent instruction may depend on whether the most recently executed instruction was misaligned.
摘要翻译：一种方法包括提供具有指令流水线的数据处理器，其中指令流水线具有多个指令流水线级，并且其中多条指令流水线级包括第一指令流水线级和第二指令流水线级。该方法还包括向指令流水线提供加载指令和数据相关指令。基于诸如ECC模式或奇偶校验模式的操作模式，数据相关指令可以在第二指令流水线级中的第一个中执行。此外，数据相关指令的执行可能取决于最近执行的指令是否不对齐。

9. 发明授权

US07941102B2 Partitioned radio-frequency apparatus and associated methods 有权
标题翻译：分频射频设备及相关方法
公开(公告)号：US07941102B2
公开(公告)日：2011-05-10
申请号：US11931656
申请日：2007-10-31
申请人： Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu Shankar Srinivasan
发明人： Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu Shankar Srinivasan
IPC分类号： H04B1/40
CPC分类号： H04B1/109 , H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064 , H04L27/2649
摘要： Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.
摘要翻译：射频（RF）设备包括接收模拟电路，其接收RF信号并且向与接收机模拟电路协作起作用的接收机数字电路提供至少一个数字信号。接收机模拟电路和接收机数字电路被分割，使得接收机模拟电路和接收机数字电路之间的干扰效应趋于降低。

10. 发明申请

US20090222648A1 SELECTIVE POSTPONEMENT OF BRANCH TARGET BUFFER (BTB) ALLOCATION 有权
标题翻译：分支目标缓冲区（BTB）分配的选择性支持
公开(公告)号：US20090222648A1
公开(公告)日：2009-09-03
申请号：US12040204
申请日：2008-02-29
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/32
CPC分类号： G06F9/3806 , G06F9/3802 , G06F9/3814 , G06F9/3844
摘要： A system and method provides branch target buffer (BTB) allocation. When a branch instruction is received, a branch target address that corresponds to the branch instruction is determined. A determination is made whether the branch target address is presently stored in a branch target buffer (BTB). When the branch target address is not presently stored in the branch target buffer, an entry in the branch target buffer is identified to receive the branch target address. A value in a field within the identified entry in the branch target buffer, such as a postponement flag (PF), is used to selectively override a replacement decision defined by predetermined branch target buffer allocation criteria. In one form, if a branch is taken, the identified entry is replaced with the branch target address in response to determining that the value in the field within the identified entry has a predetermined value.
摘要翻译：系统和方法提供分支目标缓冲区（BTB）分配。当接收到分支指令时，确定与分支指令对应的分支目标地址。确定分支目标地址是否当前存储在分支目标缓冲器（BTB）中。当分支目标地址当前不存储在分支目标缓冲器中时，识别分支目标缓冲器中的条目以接收分支目标地址。使用分支目标缓冲器中的所识别的条目中的字段中的值（诸如推迟标志（PF））来选择性地覆盖由预定分支目标缓冲器分配标准定义的替换决策。在一种形式中，如果采取分支，则响应于确定所识别的条目中的字段中的值具有预定值，将所标识的条目替换为分支目标地址。

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