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1. 发明授权

US06898343B2 Optical switching apparatus and method for fabricating 失效
标题翻译：光开关装置及其制造方法
公开(公告)号：US06898343B2
公开(公告)日：2005-05-24
申请号：US09932526
申请日：2001-08-17
申请人： Alexei Glebov , Michael Peters , Michael Lee , James Roman , David Kudzuma
发明人： Alexei Glebov , Michael Peters , Michael Lee , James Roman , David Kudzuma
IPC分类号： G02B6/12 , G02B6/13 , G02F1/31 , G02F1/313 , G02B6/42
CPC分类号： G02F1/31
摘要： A hybrid integration process for fabrication of an optical cross-connect switching apparatus. The switching element is based on the deflection of light beam in electro-optic materials by applying electric field across electrodes of an appropriate configuration. The integration process includes fabrication of a substrate (e.g. silicon substrate) with 2D imaging optics from polymeric materials (or silica), fabrication of the light deflecting element, and assembly of the deflecting element on the substrate with imaging optics. The fabrication of the light deflecting element includes fabrication of a LN (lithium niobate) block. The LN block assembled in an optical switching apparatus includes a two-dimensional waveguide formed on a surface of the LN block and an electrode on a surface of the LN block.
摘要翻译：一种用于制造光交叉连接开关装置的混合集成方法。开关元件基于通过在适当配置的电极上施加电场而在光电材料中的光束的偏转。整合过程包括使用来自聚合材料（或二氧化硅）的2D成像光学器件制造衬底（例如硅衬底），制造光偏转元件，以及使用成像光学器件将偏转元件组装在衬底上。光偏转元件的制造包括制造LN（铌酸锂）块。组装在光开关装置中的LN块包括形成在LN块表面上的二维波导和LN块表面上的电极。

2. 发明授权

US5722162A Fabrication procedure for a stable post 失效
标题翻译：一个稳定的岗位的制作程序
公开(公告)号：US5722162A
公开(公告)日：1998-03-03
申请号：US541219
申请日：1995-10-12
申请人： William T. Chou , Solomon I. Beilin , David A. Horine , David Kudzuma , Michael G. Lee , Larry Louis Moresco , Wen-chou Vincent Wang
发明人： William T. Chou , Solomon I. Beilin , David A. Horine , David Kudzuma , Michael G. Lee , Larry Louis Moresco , Wen-chou Vincent Wang
IPC分类号： G03F7/26 , H01L21/48 , H01L23/12 , H01L23/52 , H05K3/18 , H05K3/40 , H05K3/10
CPC分类号： H05K3/4007 , H01L21/4853 , H01L2924/00013 , H05K2201/0347 , H05K2201/0367 , H05K2203/0577 , Y10T29/49155 , Y10T29/49165 , Y10T29/49204
摘要： An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.
摘要翻译：通过在基板上形成第一层正性光致抗蚀剂，通过在第一层上软化烘烤该第一层并将其暴露在短时间内，用一个整体电路芯片来形成用于安装诸如集成电路芯片的微电子器件的互连柱，宽孔径面罩或简单的UV空白洪水曝光。在不显影第一层的情况下，将第二层正性抗蚀剂涂覆在第一层上，软化，然后用窄孔径掩模曝光。在第二层的软烘烤期间，光致抗蚀剂化合物中的一些活化剂扩散到第一层的暴露部分，并以这样的方式改变其溶解度，使得当这些层随后显影时，显影剂部分地削弱未曝光第一层的部分以在光致抗蚀剂中形成具有大致均匀横截面的开口。然后可以通过电镀填充该开口以产生强大的整体互连柱。

3. 发明授权

US6102710A Controlled impedance interposer substrate and method of making 失效
标题翻译：受控阻抗插入器基板及其制造方法
公开(公告)号：US6102710A
公开(公告)日：2000-08-15
申请号：US70493
申请日：1998-04-30
申请人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou Vincent Wang , Larry L. Moresco , Teruo Murase
发明人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou Vincent Wang , Larry L. Moresco , Teruo Murase
IPC分类号： H01L21/48 , H01L23/498 , H01L23/538 , H01L23/66 , H01L25/065 , H05K1/14 , H01R12/00
CPC分类号： H05K1/144 , H01L21/486 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/5385 , H01L23/5387 , H01L23/66 , H01L25/0652 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011
摘要： An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed through rigid segments and signals are routed through a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected. In another embodiment of the invention, a separate power plate is provided for carrying the power lines. Portions of the power plate, with a multilayered thin film structure thereon, are cut and folded to form interposers. Methods of making single-chip interposers are also disclosed.
摘要翻译：示出了用于将集成电路芯片安装到基板的插入器基板及其制造方法。插入器基板包括彼此基本隔离的电源路径和受控阻抗信号路径。电源通过刚性段布线，信号通过从内插器基板的上表面延伸到下表面的薄膜柔性连接器。旁路电容被并入到插入器基板中并且连接到电源，使得其非常靠近集成电路芯片。可以通过在其上形成有通孔的刚性基板上形成包括信号路径的多层薄膜结构来制造插入件，去除离开两端段的基板的中心部分，以及折叠和连接端部段，使得通孔为连接的。在本发明的另一实施例中，提供了用于承载电源线的单独的功率板。在其上具有多层薄膜结构的功率板的部分被切割和折叠以形成插入件。还公开了制造单芯片插入件的方法。

4. 发明授权

US5778529A Method of making a multichip module substrate 失效
标题翻译：制造多芯片模块基板的方法
公开(公告)号：US5778529A
公开(公告)日：1998-07-14
申请号：US651479
申请日：1996-05-22
申请人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Teruo Murase , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-Chou Vincent Wang
发明人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Teruo Murase , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-Chou Vincent Wang
IPC分类号： H01L21/48 , H01L23/473 , H01L23/498 , H01L23/538 , H01L23/66 , H01L25/065 , H05K1/14 , H01K3/10 , H05K3/10
CPC分类号： H01L21/486 , H01L21/4857 , H01L23/473 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/5385 , H01L23/66 , H01L25/0652 , H05K1/144 , H01L2224/16 , H01L2924/00013 , H01L2924/01019 , H01L2924/01078 , H01L2924/09701 , H01L2924/3011 , Y10T29/49155 , Y10T29/49165 , Y10T29/49204
摘要： A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.
摘要翻译：公开了一种用于三维多芯片模块的多芯片模块基板及其制造方法。衬底包括薄膜结构，用于将信号路由到集成电路芯片上并从集成电路芯片路由到刚性支撑基底上。在支撑基体中形成孔，露出薄膜结构的下侧，从而允许将高密度连接器安装在薄膜结构的两个表面上，大大增强了在芯片模块中的相邻基板之间传递信号的能力。这避免了将信号路由通过刚性支撑底座或薄膜结构的边缘的需要。不需要高连接密度的电源和接地路径通过支持底座的低阻抗路径。优选地，薄膜结构由诸如铜的图案化金属的交替层和诸如聚酰亚胺的低介电有机聚合物制成。

5. 发明授权

US5660957A Electron-beam treatment procedure for patterned mask layers 失效
标题翻译：图案化掩模层的电子束处理程序
公开(公告)号：US5660957A
公开(公告)日：1997-08-26
申请号：US649999
申请日：1996-05-16
申请人： William T. Chou , Solomon I. Beilin , David Kudzuma , Wen-chou Vincent Wang
发明人： William T. Chou , Solomon I. Beilin , David Kudzuma , Wen-chou Vincent Wang
IPC分类号： G03F7/40 , H01L21/027 , G03F9/00
CPC分类号： G03F7/40 , H01L21/0273
摘要： Methods for pretreating patterned masks layers, such as photoresist masks, with electron-beam radiation for use in high temperature processes are disclosed. The electron-beam exposure deactivates compounds within the mask material which would ordinarily decompose and produce gasses within the photoresist layer. The gasses cause blistering in the untreated photoresist layer, which in turn degrades the dimensional integrity of the untreated layer.
摘要翻译：公开了用于在高温过程中使用的电子束辐射来预处理图案化掩模层（例如光致抗蚀剂掩模）的方法。电子束曝光使通常在光致抗蚀剂层内分解和产生气体的掩模材料内的化合物失活。气体在未处理的光致抗蚀剂层中引起起泡，这进而降低未处理层的尺寸完整性。

6. 发明授权

US5930890A Structure and fabrication procedure for a stable post 失效
标题翻译：稳定桩的结构和制造程序
公开(公告)号：US5930890A
公开(公告)日：1999-08-03
申请号：US858192
申请日：1997-04-21
申请人： William T. Chou , Solomon I. Beilin , David A. Horine , David Kudzuma , Michael G. Lee , Larry Louis Moresco , Wen-chou Vincent Wang
发明人： William T. Chou , Solomon I. Beilin , David A. Horine , David Kudzuma , Michael G. Lee , Larry Louis Moresco , Wen-chou Vincent Wang
IPC分类号： G03F7/26 , H01L21/48 , H01L23/12 , H01L23/52 , H05K3/18 , H05K3/40 , H01K3/10
CPC分类号： H05K3/4007 , H01L21/4853 , H01L2924/00013 , H05K2201/0347 , H05K2201/0367 , H05K2203/0577 , Y10T29/49155 , Y10T29/49165 , Y10T29/49204
摘要： An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.
摘要翻译：通过在基板上形成第一层正性光致抗蚀剂，通过在第一层上软化烘烤该第一层并将其暴露在短时间内，用一个整体电路芯片来形成用于安装诸如集成电路芯片的微电子器件的互连柱，宽孔径面罩或简单的UV空白洪水曝光。在不显影第一层的情况下，将第二层正性抗蚀剂涂覆在第一层上，软化，然后用窄孔径掩模曝光。在第二层的软烘烤期间，光致抗蚀剂化合物中的一些活化剂扩散到第一层的暴露部分，并以这样的方式改变其溶解度，使得当这些层随后显影时，显影剂部分地削弱未曝光第一层的部分以在光致抗蚀剂中形成具有大致均匀横截面的开口。然后可以通过电镀填充该开口以产生强大的整体互连柱。

7. 发明授权

US5854534A Controlled impedence interposer substrate 失效
标题翻译：受控阻抗插入器基板
公开(公告)号：US5854534A
公开(公告)日：1998-12-29
申请号：US559369
申请日：1995-11-16
申请人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou Vincent Wang , Larry L. Moresco , Teruo Murase
发明人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou Vincent Wang , Larry L. Moresco , Teruo Murase
IPC分类号： H01L21/48 , H01L23/498 , H01L23/538 , H01L23/66 , H01L25/065 , H05K1/14 , H01L23/52 , H01L23/04 , H01L23/053 , H01L23/34
CPC分类号： H05K1/144 , H01L21/486 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/5385 , H01L23/5387 , H01L23/66 , H01L25/0652 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011
摘要： An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed though rigid segments and signals are routed though a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected. In another embodiment of the invention, a separate power plate is provided for carrying the power lines. Portions of the power plate, with a multilayered thin film structure thereon, are cut and folded to form interposers. Methods of making single-chip interposers are also disclosed.
摘要翻译：示出了用于将集成电路芯片安装到基板的插入器基板及其制造方法。插入器基板包括彼此基本隔离的电源路径和受控阻抗信号路径。电源通过刚性段传送，信号通过薄膜柔性连接器布线，该连接器从插入器基板的上表面延伸到下表面。旁路电容被并入到插入器基板中并且连接到电源，使得其非常靠近集成电路芯片。可以通过在其上形成有通孔的刚性基板上形成包括信号路径的多层薄膜结构来制造插入件，去除离开两端段的基板的中心部分，以及折叠和连接端部段，使得通孔为连接的。在本发明的另一实施例中，提供了用于承载电源线的单独的功率板。在其上具有多层薄膜结构的功率板的部分被切割和折叠以形成插入件。还公开了制造单芯片插入件的方法。

8. 发明授权

US5544017A Multichip module substrate 失效
标题翻译：多芯片模块基板
公开(公告)号：US5544017A
公开(公告)日：1996-08-06
申请号：US277163
申请日：1994-07-19
申请人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Teruo Murase , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou V. Wang
发明人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Teruo Murase , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou V. Wang
IPC分类号： H01L21/48 , H01L23/473 , H01L23/498 , H01L23/538 , H01L23/66 , H01L25/065 , H05K1/14
CPC分类号： H01L21/486 , H01L21/4857 , H01L23/473 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/5385 , H01L23/66 , H01L25/0652 , H05K1/144 , H01L2224/16 , H01L2924/00013 , H01L2924/01019 , H01L2924/01078 , H01L2924/09701 , H01L2924/3011 , Y10T29/49155 , Y10T29/49165 , Y10T29/49204
摘要： A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.
摘要翻译：公开了一种用于三维多芯片模块的多芯片模块基板及其制造方法。衬底包括薄膜结构，用于将信号路由到集成电路芯片上并从集成电路芯片路由到刚性支撑基底上。在支撑基体中形成孔，露出薄膜结构的下侧，从而允许将高密度连接器安装在薄膜结构的两个表面上，大大增强了在芯片模块中的相邻基板之间传递信号的能力。这避免了将信号路由通过刚性支撑底座或薄膜结构的边缘的需要。不需要高连接密度的电源和接地路径通过支持底座的低阻抗路径。优选地，薄膜结构由诸如铜的图案化金属的交替层和诸如聚酰亚胺的低介电有机聚合物制成。

9. 发明授权

US5419038A Method for fabricating thin-film interconnector 失效
标题翻译：制造薄膜互连器的方法
公开(公告)号：US5419038A
公开(公告)日：1995-05-30
申请号：US78461
申请日：1993-06-17
申请人： Wen-chou V. Wang , Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy
发明人： Wen-chou V. Wang , Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy
IPC分类号： H05K1/11 , H05K1/14 , H05K3/00 , H05K3/46 , H05K3/36
CPC分类号： H05K3/4691 , H05K2201/0394 , H05K3/002 , H05K3/0023 , H05K3/0041 , H05K3/467 , Y10T29/49124 , Y10T29/49126 , Y10T29/49165
摘要： A three dimensional thin-film interconnector is fabricated by depositing a dielectric layer onto the surface of a substrate, depositing a layer of conductive material onto the dielectric layer to form a signal plane, depositing a dielectric layer onto the surface of the signal plane, forming a plurality of through holes in the dielectric layer that extend to the signal plane, and filling the through holes with an electrically conductive material to form vias. The sequence of forming a signal plane, depositing a dielectric layer, forming a plurality of through holes, and filling the through holes is repeated until a predetermined number of signal planes and a predetermined arrangement of vias are obtained. The through holes are formed at locations in the dielectric layers corresponding to both predetermined electrical connections and the vias in a preceding dielectric layer. The signal planes are formed at different locations on the substrate. The sequence of signal planes and dielectric layers at the same location on the substrate form a signal plane set which defines a connector. Contact pads are deposited onto the surface of a final dielectric layer and electrically connect with each via. Wires are used to electrically connect the contact pads of one connector to corresponding contact pads of another connector. A portion of the substrate and dielectric layers not comprising a signal plane set is removed, forming electrical connectors flexibly attached by the plurality of wires.
摘要翻译：通过在衬底的表面上沉积介电层来制造三维薄膜互连器，在电介质层上沉积导电材料层以形成信号平面，在信号面的表面上沉积电介质层，形成电介质层中的多个通孔延伸到信号平面，并用导电材料填充通孔以形成通孔。重复形成信号平面，沉积介电层，形成多个通孔和填充通孔的顺序，直到获得预定数量的信号面和通孔的预定布置。通孔形成在电介质层中对应于先前电介质层中的预定电连接和通路两者的位置处。信号面形成在基板上的不同位置。基板上相同位置处的信号平面和电介质层的顺序形成了限定连接器的信号平面组。接触焊盘沉积在最终电介质层的表面上并与每个通孔电连接。电线用于将一个连接器的接触焊盘电连接到另一个连接器的相应接触焊盘。除去不包括信号平面组的衬底和电介质层的一部分，形成由多个电线柔性附接的电连接器。

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