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    • 10. 发明申请
    • Chemical mechanical polishing techniques for integrated circuit fabrication
    • 用于集成电路制造的化学机械抛光技术
    • US20070082479A1
    • 2007-04-12
    • US11245677
    • 2005-10-06
    • Deenesh PadhiGirish Dixit
    • Deenesh PadhiGirish Dixit
    • H01L21/4763
    • H01L21/76843H01L21/76819H01L21/7684H01L22/12H01L2924/0002H01L2924/00
    • The present invention provides methods for fabricating horizontal interconnect lines for use in semiconductor wafer fabrication. A dielectric layer is deposited on a dielectric stack having a planarized top surface. The dielectric layer is not planarized at this stage of the process. A pre-planarizing thickness profile of the non-planarized dielectric layer is determined and recorded. An interconnect line trench is then etched through the dielectric layer. A sandwich layer including a conductive Cu diffusion barrier layer and a Cu seed layer is deposited in the trench and on the dielectric layer. A Cu comprising metal is deposited in the sandwich lined trench. A Cu metal overburden is thereby deposited on the section of the sandwich layer that is positioned on the dielectric layer. A first CMP process is used to remove the Cu overburden and the Cu seed layer that is formed in the sandwich layer portion on the dielectric layer. A second CMP process is utilized wherein the pre-planarizing thickness profile is employed to remove the Cu barrier layer from the top surface of the dielectric layer, the second CMP process is then continued by planarizing the dielectric layer to form a substantially uniform flat surface having a substantially uniform thickness which is substantially equal to a predetermined design thickness. The second CMP process thereby results in fabricating a dielectric layer wherein substantially all interconnect lines have a substantially uniform thickness that is substantially equal to the design thickness for the dielectric layer.
    • 本发明提供用于制造用于半导体晶片制造的水平互连线的方法。 介电层沉积在具有平坦化顶表面的电介质叠层上。 在该过程的这个阶段,电介质层不被平坦化。 确定并记录非平面化电介质层的预平面化厚度分布。 然后通过介电层蚀刻互连线沟槽。 包含导电性Cu扩散阻挡层和Cu籽晶层的夹层被沉积在沟槽和电介质层上。 包含金属的Cu沉积在夹层衬里的沟槽中。 因此,在位于电介质层上的夹层的部分上沉积Cu金属覆盖层。 使用第一CMP工艺来去除在电介质层上的夹层结构部分中形成的Cu覆盖层和Cu籽晶层。 使用第二CMP工艺,其中使用预平面化厚度轮廓来从电介质层的顶表面去除Cu阻挡层,然后通过平坦化介电层来继续进行第二CMP工艺以形成基本上均匀的平坦表面,其具有 基本均匀的厚度,其基本上等于预定的设计厚度。 因此,第二CMP工艺导致制造介电层,其中基本上所有的互连线具有基本上等于介电层的设计厚度的基本均匀的厚度。